MC68HC901 Datasheet, PDF (20/73 Pages) Motorola, Inc – Multi-Function Peripheral

SECTION 3
BUS OPERATION
The following paragraphs describe control signals and the bus operation during data
transfer, interrupt acknowledge, and reset operations.
3.1 DATA TRANSFER OPERATIONS
Transfer of data between devices involves the following pins:
• Register Select Bus – RS1 through RS5
• Data Bus – D0 through D7
• Control Signals
The address and data buses are separate parallel buses used to transfer data using an
asynchronous bus structure. In all cases, the bus master assumes responsibility for
deskewing all signals it issues at both the start and end of a cycle. Additionally, the bus
master is responsible for deskewing the acknowledge and data signals from the peripheral
devices.
3.1.1 Read Cycle
To read an MFP register, CS and DS must be asserted, and R/W must be high. The MFP
will place the contents of the register which is selected by the register select bus (RS1
through RS5) on the data bus (D0 through D7) and then assert DTACK. The register
addresses are shown in Table 1-1.
After the processor has latched the data, it negates DS. The negation of either CS or DS will
terminate the read operation. The MFP will drive DTACK high and place it and the data bus
in the high-impedance state. The timing for a read cycle is shown in Figure 3-1. Refer to
Section 8.7 AC Electrical Characteristics for actual timing numbers.
MOTOROLA
MC68HC901 USER’S MANUAL
3-1