MC68307V Datasheet, PDF (4/34 Pages) Motorola, Inc – Technical Summary Integrated Multiple-Bus Processor

MC68307 ARCHITECTURE
To improve total system throughput and reduce part count, board size and cost of system implementation, the
MC68307 integrates a powerful processor, intelligent peripheral modules, and typical system interface logic.
These functions include the SIM07, timers, UART, M-bus interface, and 8051-compatible bus interface.
The EC000 processor core communicates with these modules via an internal bus, providing the opportunity for
fully synchronized communication between all modules and allowing interrupts to be handled in parallel with data
transfers, greatly improving system performance.
STATIC EC000 CORE
The EC000 core is a core implementation of the MC68000 32-bit microprocessor architecture. The features of
the EC000 core processor include:
• Low power, static HCMOS implementation
• 24-bit address bus, 16-bit data bus
• Seventeen 32-bit data and address registers
• 56 powerful instruction types that support high level development languages
• 14 addressing modes and five main data types
• Seven priority levels for interrupt control
The EC000 core is completely upward user code-compatible with all other members of the M68000
microprocessor families and thus has access to a broad base of established real-time kernels, operating
systems, languages, applications, and development tools.
EC000 Core Programming Model
The EC000 core offers sixteen 32-bit registers and a 32-bit program counter (see Figure 2). The first eight
registers (D7–D0) are used as data registers for byte (8-bit), word (16-bit) and long-word (32-bit) operations.
Because the use of the data registers will affect the condition code register (indicating negative number, carry,
and overflow conditions) they are primarily used for data manipulation. The second set of seven registers (A6–
A0) and the user stack pointer (USP) may be used as software stack pointers and base address registers. These
registers can be used for word and long-word operations and do not affect the condition code register. All of the
registers (D7–D0 and A6–A0) may be used as index registers.
In supervisor mode, the upper byte of the status register (SR) and the supervisor stack pointer (SSP) are also
available to the programmer. These registers are shown in Figure 3.
The SR (refer to Figure 4) contains the interrupt mask (seven levels available) as well as the following condition
codes: extend (X), negative (N), zero (Z), overflow (V), and carry (C). Additional status bits indicate whether the
processor is in trace mode (T-bit) and in supervisor or user state (S-bit).
4
MC68307 TECHNICAL INFORMATION
MOTOROLA