MC68307V Datasheet, PDF (25/34 Pages) Motorola, Inc – Technical Summary Integrated Multiple-Bus Processor

CLK
A23–A1
CSx, AS
(NOTE 2)
LDS / UDS
R/W
(NOTE 2)
DTACK
D15–D0
BR
(NOTE 3)
HALT / RESET
ASYNCHRONOUS
INPUTS
(NOTE 1)
S0 S1 S2 S3 S4 S5 S6 S7
8
6
21
15
9
11A
17
18
11
20A
20
22
14
9
14A
13
15A
47
55
26
7
23
48
47
47
47
32
32
56
47
12
28
53
25
NOTES:
1. Setup time (#47) for asynchronous inputs (HALT, RESET, BR, BGACK, DTACK) guarantees
their recognition at the next falling edge of the clock.
2. Because of loading variations, R/W may be valid after AS even though both are initiated by the rising edge
of S2 (specification #20A).
3. BR need fall at this time only to ensure being recognized at the end of the bus cycle.
Figure 9. Write Cycle Timing Diagram
MOTOROLA
MC68307 TECHNICAL INFORMATION
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