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MC68307V Datasheet, PDF (2/34 Pages) Motorola, Inc – Technical Summary Integrated Multiple-Bus Processor | |||
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The main features of the MC68307 include:
⢠Static EC000 Core ProcessorâIdentical to MC68EC000 Microprocessor
â Full compatibility with MC68000 and MC68EC000
â 24-bit address bus, for 16-Mbyte off-chip address space
â 16-bit on-chip data bus for MC68000 bus operations
â Static design allows processor clock to be stopped providing dramatic power savings
â 2.4 MIPS performance at 16.67-MHz processor clock
⢠External M68000 Bus Interface with Dynamic Bus Sizing for 8-bit and 16-bit Data Ports
⢠External 8-Bit Data Bus Interface (8051-Compatible)
⢠M-Bus Module
â Provides interchip bus interface for EEPROMs, LCD controllers, A/D converters, etc.
â Compatible with industry-standard I2C bus
â Master or slave operation modes, supports multiple masters
â Automatic interrupt generation with programmable level
â Software-programmable clock frequency
â Data rates from 4â100 Kbit/s above 3.0-MHz system clock
⢠Universal Asynchronous Receiver/Transmitter (UART) Module
â Flexible baud rate generator
â Based on MC68681 Dual Universal Asynchronous Receiver/Transmitter (DUART) programming
model
â 5 Mbits/s maximum transfer rate at 16.67-MHz system clock
â Automatic interrupt generation with programmable level
â Modem control signals available (CTS,RTS)
⢠Timer Module
â Dual channel 16-bit general purpose counter/timer
â Multimode operation, independent capture/compare registers
â Automatic interrupt generation with programmable level
â Third 16-bit timer configured as a software watchdog
â 60-ns resolution at 16.67-MHz system clock
â Each timer has an input and an output pin
⢠System Integration Module (SIM07), Incorporating Many Functions Typically Relegated to External Pro-
grammable Array Logic (PALs), Transistor-Transistor Logic (TTL), and ASICs, such as:
â System configuration, programmable address mapping
â System protection by hardware watchdog logic
â Power-down mode control, programmable processor clock driver
â Four programmable chip selects with wait state generation logic
â Three simple peripheral chip selects
â Parallel input/output ports, some with interrupt capability
â Programmed interrupt vector response for on-chip peripheral modules
â IEEE 1149.1 boundary scan test access port (JTAG)
⢠Operation from DC to 16.67 MHz (Processor Clock)
⢠Operating Voltages of 3.3V ± 0.3V and 5V ± 0.5V
⢠Compact 100-Lead Quad Flat Pack (QFP) Package
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MC68307 TECHNICAL INFORMATION
MOTOROLA
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