MC68307V Datasheet, PDF (14/34 Pages) Motorola, Inc – Technical Summary Integrated Multiple-Bus Processor

M-BUS INTERFACE MODULE
The M-bus is a two-wire, bidirectional serial bus which provides a simple and efficient means of data exchange
between devices; it is fully compatible with the I²C bus standard. The maximum data rate is limited to 100 kbit/s
at 16.67-MHz system clock speed. The maximum communication length and the number of devices that can be
connected are limited by a maximum bus capacitance of 400 pF. The serial bit clock frequency of the M-bus is
programmable and ranges from 3830 Hz to 757 kHz for a 16.67-MHz internal operating frequency.
The M-bus system is a true multimaster bus including collision detection and arbitration to prevent data corruption
(when two or more masters intend to control the bus simultaneously). The M-bus system uses the SDA and SCL
signals for data transfer. All devices connected to the M-bus interface must have open-drain or open-collector
output; a logic AND function is exercised in both lines with pull-up resistors.
The features of the M-bus include:
• Fully compatible with I²C bus standard
• Multimaster operation
• Software programmable for one of 32 different serial clock frequencies
• Software selectable acknowledge bit
• Interrupt driven byte-by-byte data transfer
• Arbitration-lost driven interrupt with automatic mode switching from master to slave
• Calling address identification interrupt
• Generate/detect the START or STOP signal
• Repeated START signal generation
• Generate/recognize the acknowledge bit
• Bus busy detection
M-Bus Programming Model
The programming model for the M-bus module is listed in Table 9. The FC (function code) column indicates
whether a register is restricted to supervisor access (S) or programmable to exist in either supervisor or user
space (S/U). The address column contains the offset from the base address (MBASE) contained in the SIM07
MBAR.
Table 9. M-Bus Module Registers
Address
FC
Register Name
MBASE+$141 S/U Do not access byte $140 M-bus address register (MADR)
MBASE+$143 S/U Do not access byte $142 M-bus frequency divider register (MFDR)
MBASE+$145 S/U Do not access byte $144
M-bus control register (MBCR)
MBASE+$147 S/U Do not access byte $146
M-bus status register (MBSR)
MBASE+$149 S/U Do not access byte $148 M-bus data I/O register (MBDR)
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MC68307 TECHNICAL INFORMATION
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