MC68307V Datasheet, PDF (24/34 Pages) Motorola, Inc – Technical Summary Integrated Multiple-Bus Processor

CLK
A23–A1
CSx, AS
LDS / UDS
R/W
S0 S1 S2 S3 S4 S5 S6 S7
8
6
12
15
14
13
11
11A
9
47
28
DTACK
D15–D0
27
29
31
47
29A
BR
(NOTE 2)
HALT / RESET
47
47
32
32
56
47
ASYNCHRONOUS
INPUTS
(NOTE 1)
NOTES:
1. Setup time (#47) for asynchronous inputs (HALT, RESET, BR, BGACK, DTACK) guarantees
their recognition at the next falling edge of the clock.
2. BR need fall at this time only to ensure being recognized at the end of the bus cycle.
Figure 8. Read Cycle Timing Diagram
24
MC68307 TECHNICAL INFORMATION
MOTOROLA