MC68307V Datasheet, PDF (23/34 Pages) Motorola, Inc – Technical Summary Integrated Multiple-Bus Processor

PRELIMINARY AC TIMING SPECIFICATIONS
(V_CC = 5.0V ± 0.5V or 3.3Vdc ± 0.3V; GND = 0Vdc; T_A = T_L to T_H) (See Figures 8–10)
3.3 V
5V
Num
Characteristic
8.33 MHz 16.67 MHz Unit
Min Max Min Max
55 R/W asserted to data bus impedance change
56^e HALT/RESET pulse width
40 — 20 — ns
10 — 10 — Clks
57 BGACK negated to AS, CSx, LDS, UDS, R/W driven
1.5 — 1.5 — Clks
58 BR negated to AS, CSx, LDS, UDS, R/W driven
1.5 — 1.5 — Clks
NOTES:
a. For a loading capacitance of less than or equal to 50 pF, subtract 5 ns from the value given in the maximum
columns.
b. Actual value depends on clock period.
c. When AS, CSx and R/W are equally loaded (±20%), subtract 5 ns from the values given in these columns.
d. If the asynchronous input setup time (#47) requirement is satisfied for DTACK, the DTACK asserted to data
setup time (#31) requirement can be ignored. The data must only satisfy the data-in to clock low setup time
(#27) for the following clock cycle.
e. For power-up, the MC68307 must be held in the reset state for 128 clock cycles after CLK and V_CC become
stable to allow stabilization of on-chip circuitry. After the system is powered up, #56 refers to the minimum
pulse width required to reset the controller.
.
MOTOROLA
MC68307 TECHNICAL INFORMATION
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