English
Language : 

MC68307V Datasheet, PDF (1/34 Pages) Motorola, Inc – Technical Summary Integrated Multiple-Bus Processor
MOTOROLA (Parts Not Suitable for New Designs)
SEMICONDUCTOR
TECHNICAL INFORMATION
Order this document by
MC68307/D
MC68307
MC68307V
Technical Summary
Integrated Multiple-Bus Processor
The MC68307 is an integrated processor combining a static 68EC000 processor with multiple interchip bus
interfaces. The MC68307 is designed to provide optimal integration and performance for applications such as
digital cordless telephones, portable measuring equipment, and point-of-sale terminals. By providing 3.3 V,
static operation in a small package, the MC68307 delivers cost-effective performance to handheld, battery-
powered applications.
The MC68307 (shown in Figure 1) contains a static EC000 core processor, multiple bus interfaces, a serial
channel, two timers, and common system glue logic. The multiple bus interfaces include: dynamic 68000 bus,
8051 bus, and Motorola bus (M-bus) or I2C bus1. The dynamically sized 68000 bus allows 16-bit performance
out of static random access memory (SRAM) while still providing a low-cost interface to an 8-bit read-only
memory (ROM). The 8051 bus interfaces gluelessly to 8051-type devices and allows the reuse of application-
specific integrated circuits (ASICs) designed for this industry standard bus. The M-bus is an industry standard
2-wire interface which provides efficient communications with peripherals such as EEPROM, analog/digital (A/
D) converters, and liquid crystal display (LCD) drivers. Thus, the MC68307 interfaces gluelessly to boot ROM,
SRAM, 8051 devices, M-bus devices, and memory-mapped peripherals. The MC68307 also incorporates a
slave mode which allows the EC000 core to be turned off, providing a 3.3-V static, low-power multi-function
peripheral for higher performance M68000 family processors.
SYSTEM INTEGRATION MODULE
(SIM07)
8/16-BIT M68000
BUS INTERFACE
8051 BUS INTERFACE
CHIP SELECT AND DTACK
INTERRUPT
CONTROLLER
PROCESSOR CONTROL, CLOCK
AND LOW POWER
SYSTEM PROTECTION
PARALLEL I/O PORTS
JTAG PORT
STATIC EC000 CORE PROCESSOR
DYNAMIC BUS SIZING EXTENSION
68000 INTERNAL BUS
M-BUS
MODULE
UART
SERIAL I/O
DUAL
TIMER
MODULE
Figure 1. MC68307 Block Diagram
1. I2C bus is a proprietary Philips interface bus.
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
© MOTOROLA, 1993
Thi d
t
t d ith F M k 4 0 2