MC68307V Datasheet, PDF (20/34 Pages) Motorola, Inc – Technical Summary Integrated Multiple-Bus Processor

DRIVE
TO 2.4 V
2.0 V
CLK
DRIVE TO
0.5 V
A
B
OUTPUTS(1) CLK
VALID ^{2.0 V}
OUTPUT ⁿ _{0.8 V}
OUTPUTS(2) CLK
2.0 V
0.8 V
0.8 V
2.0 V _VALID
0.8 V ^{OUTPUT n + 1}
A
B
VALID ^{2.0 V}
OUTPUT n
0.8 V
2.0 V _VALID
0.8 V ^{OUTPUT n+1}
INPUTS(3) CLK
DRIVE TO
2.4 V
DRIVE TO
0.5 V
INPUTS(4) CLK
C
D
2.0 V
VALID
2.0 V
0.8 V
INPUT
0.8 V
C
D
2.0 V
VALID
2.0 V
0.8 V
INPUT
0.8 V
ALL SIGNALS(5)
2.0 V
0.8 V
E
F
2.0 V
0.8 V
NOTES:
1. This output timing is applicable to all parameters specified relative to the rising edge of the clock.
2. This output timing is applicable to all parameters specified relative to the falling edge of the clock.
3. This input timing is applicable to all parameters specified relative to the rising edge of the clock.
4. This input timing is applicable to all parameters specified relative to the falling edge of the clock.
5. This timing is applicable to all parameters specified relative to the assertion/negation of another signal.
LEGEND:
A. Maximum output delay specification.
B. Minimum output hold time.
C. Minimum input setup time specification.
D. Minimum input hold time specification.
E. Signal valid to signal valid specification (maximum or minimum).
F. Signal valid to signal invalid specification (maximum or minimum).
Figure 6. Drive Levels and Test Points for AC Specifications
DRIVE
TO 2.4 V
DRIVE
TO 0.5 V
20
MC68307 TECHNICAL INFORMATION
MOTOROLA