MC68307V Datasheet, PDF (26/34 Pages) Motorola, Inc – Technical Summary Integrated Multiple-Bus Processor

CLK
Strobes
and
R/W
BR
BGACK
BG
35
33
38
36
37
46
34
39
Figure 10. Bus Arbitration Timing
PRELIMINARY 8051 BUS INTERFACE MODULE
AC ELECTRICAL SPECIFICATIONS
(V_CC = 5.0V ± 0.5V or 3.3Vdc ± 0.3V; GND = 0Vdc; T_A = T_L to T_H) (See Figures 11 and 12)
3.3 V
5V
Symbol
Characteristic
8 MHz
16.67 MHz
Min
Max
Min
Max
t_cyc Cycle time
120
—
60
—
TLHLL ALE pulse width
2 x t_cyc – 40
—
2 x t_cyc – 40
—
TAVLL Address valid to ALE low
t_cyc – 40
—
t_cyc – 40
—
TLLAX Address hold after ALE low
t_cyc – 35
—
t_cyc – 35
—
TRLRH _{RD pulse width}^a
5 x t_cyc
—
5 x t_cyc
—8051
TWLWH _{WR pulse width}⁽¹⁾
5 x t_cyc
—
5 x t_cyc
—
TRLDV _{RD low to valid data in}⁽¹⁾
—
5 x t_cyc – 165
—
5 x t_cyc – 165
TRHDX Data hold after RD
0
—
0
—
TRHDZ Data float after RD
—
0.5 x t_cyc
—
0.5 x t_cyc
TLLDV _{ALE low to valid data in}⁽¹⁾
—
8 x t_cyc – 150
—
8 x t_cyc – 150
TAVDV _{Address to valid data in}⁽¹⁾
—
9 x t_cyc – 165
—
9 x t_cyc – 165
TLLWL ALE low to RD or WR low
3 x t_cyc– 50 3 x t_cyc + 50 3 x t_cyc– 50 3 x t_cyc + 50
TAVWL Address to RD low or WR low
4 x t_cyc – 130
—
4 x t_cyc – 130
—
TQVWX Data valid to WR transition
t_cyc – 60
—
t_cyc – 60
—
TQVWH _{Data valid to WR high}⁽¹⁾
7 x t_cyc– 150
—
7 x t_cyc– 150
—
TWHQX Data held after WR
t_cyc– 50
—
t_cyc– 50
—
TRLAZ RD low to address float
—
—
—
—
TWHLH RD or WR high to ALE high
t_cyc– 40
t_cyc+ 50
t_cyc– 40
t_cyc+ 50
NOTE:
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
a. Wait states can be added.
26
MC68307 TECHNICAL INFORMATION
MOTOROLA