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MC68HC908GZ16 Datasheet, PDF (291/314 Pages) Motorola, Inc – Microcontrollers
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5-Vdc Electrical Characteristics
Characteristic(1)
Symbol
Min
Typ(2)
Max
Unit
Input high voltage
All ports, IRQ, RST, OSC1
VIH
0.7 × VDD
—
VDD
V
Input low voltage
All ports, IRQ, RST, OSC1
VIL
VSS
—
0.2 × VDD
V
VDD supply current
Run(3)
Wait(4)
Stop(5)
25°C
25°C with TBM enabled(6)
25°C with LVI and TBM enabled(6)
–40°C to 125°C with TBM enabled(6)
–40°C to 125°C with LVI and TBM enabled(6)
—
20
30
mA
—
6
12
mA
IDD
—
3
—
µA
—
20
—
µA
—
300
—
µA
—
50
—
µA
—
500
—
µA
DC injection current, all ports
IINJ
–2
—
+2
mA
Total dc current injection (sum of all I/O)
IINJTOT
–25
—
+25
mA
I/O ports Hi-Z leakage current(7)
IIL
–10
—
+10
µA
Input current
IIn
–1
—
+1
µA
Pullup resistors (as input only)
Ports PTA7/KBD7–PTA0/KBD0, PTC6–PTC0/CANTX,
RPU
PTD7/T2CH1–PTD0/SS
20
45
65
kΩ
Capacitance
Ports (as input or output)
Monitor mode entry voltage
Low-voltage inhibit, trip falling voltage
Low-voltage inhibit, trip rising voltage
Low-voltage inhibit reset/recover hysteresis
(VTRIPF + VHYS = VTRIPR)
POR rearm voltage(8)
COut
CIn
—
—
—
—
12
8
pF
VTST
VDD + 2.5
—
VDD + 4.0
V
VTRIPF
3.90
4.25
4.50
V
VTRIPR
4.20
4.35
4.60
V
VHYS
—
100
—
mV
VPOR
0
—
100
mV
POR reset voltage(9)
VPORRST
0
700
800
mV
POR rise time ramp rate(10)
RPOR
0.035
—
—
V/ms
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TA (min) to TA (max), unless otherwise noted
2. Typical values reflect average measurements at midpoint of voltage range, 25°C only.
3. Run (operating) IDD measured using external square wave clock source (fOSC = 32 MHz). All inputs 0.2 V from rail. No dc
loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly
affects run IDD. Measured with all modules enabled.
4. Wait IDD measured using external square wave clock source (fOSC = 32 MHz). All inputs 0.2 V from rail. No dc loads. Less
than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait
IDD. Measured with CGM and LVI enabled.
5. Stop IDD is measured with OSC1 = VSS. All inputs 0.2 V from rail. No dc loads. Less than 100 pF on all outputs. All ports
configured as inputs. Typical values at midpoint of voltage range, 25°C only.
6. Stop IDD with TBM enabled is measured using an external square wave clock source (fOSC = 32 MHz). All inputs 0.2 V
from rail. No dc loads. Less than 100 pF on all outputs. All inputs configured as inputs.
7. Pullups and pulldowns are disabled. Port B leakage is specified in 21.10 5.0-Volt ADC Characteristics.
8. Maximum is highest voltage that POR is guaranteed.
9. Maximum is highest voltage that POR is possible.
10. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum
VDD is reached.
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 1
Freescale Semiconductor
291
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