MC68HC908GZ16 Datasheet, PDF (208/314 Pages) Motorola, Inc – Microcontrollers

Enhanced Serial Communications Interface (ESCI) Module
15.8.8 ESCI Prescaler Register
The ESCI prescaler register (SCPSC) together with the ESCI baud rate register selects the baud rate for
both the receiver and the transmitter.
NOTE
There are two prescalers available to adjust the baud rate. One in the ESCI
baud rate register and one in the ESCI prescaler register.
Address:
Read:
Write:
Reset:
$0009
Bit 7
PDS2
0
6
PDS1
0
5
PDS0
0
4
PSSB4
0
3
PSSB3
0
2
PSSB2
0
1
PSSB1
0
Bit 0
PSSB0
0
Figure 15-18. ESCI Prescaler Register (SCPSC)
PDS2–PDS0 — Prescaler Divisor Select Bits
These read/write bits select the prescaler divisor as shown in Table 15-9. Reset clears PDS2–PDS0.
NOTE
The setting of ‘000’ will bypass this prescaler. It is not recommended to
bypass the prescaler while ENSCI is set, because the switching is not glitch
free.
Table 15-9. ESCI Prescaler Division Ratio
PS[2:1:0]
000
001
010
011
100
101
110
111
Prescaler Divisor (PD)
Bypass this prescaler
2
3
4
5
6
7
8
PSSB4–PSSB0 — Clock Insertion Select Bits
These read/write bits select the number of clocks inserted in each 32 output cycle frame to achieve
more timing resolution on the average prescaler frequency as shown in Table 15-10. Reset clears
PSSB4–PSSB0.
Use the following formula to calculate the ESCI baud rate:
Frequency of the SCI clock source
Baud rate = _{64 x BPD x BD x (PD + PDFA)}
where:
Frequency of the SCI clock source = f_Bus or CGMXCLK (selected by
ESCIBDSRC in the CONFIG2 register)
BPD = Baud rate register prescaler divisor
BD = Baud rate divisor
PD = Prescaler divisor
PDFA = Prescaler divisor fine adjust
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 1
208
Freescale Semiconductor