MC68HC908GZ16 Datasheet, PDF (178/314 Pages) Motorola, Inc – Microcontrollers

Resets and Interrupts
14.3.2.3 IRQ Pin
A logic 0 on the IRQ1 pin latches an external interrupt request.
14.3.2.4 Clock Generator (CGM)
The CGM can generate a CPU interrupt request every time the phase-locked loop circuit (PLL) enters or
leaves the locked state. When the LOCK bit changes state, the PLL flag (PLLF) is set. The PLL interrupt
enable bit (PLLIE) enables PLLF CPU interrupt requests. LOCK is in the PLL bandwidth control register.
PLLF is in the PLL control register.
14.3.2.5 Timer Interface Module 1 (TIM1)
TIM1 CPU interrupt sources:
• TIM1 overflow flag (TOF) — The TOF bit is set when the TIM1 counter value rolls over to $0000
after matching the value in the TIM1 counter modulo registers. The TIM1 overflow interrupt enable
bit, TOIE, enables TIM1 overflow CPU interrupt requests. TOF and TOIE are in the TIM1 status
and control register.
• TIM1 channel flags (CH1F–CH0F) — The CHxF bit is set when an input capture or output compare
occurs on channel x. The channel x interrupt enable bit, CHxIE, enables channel x TIM1 CPU
interrupt requests. CHxF and CHxIE are in the TIM1 channel x status and control register.
14.3.2.6 Timer Interface Module 2 (TIM2)
TIM2 CPU interrupt sources:
• TIM2 overflow flag (TOF) — The TOF bit is set when the TIM2 counter value rolls over to $0000
after matching the value in the TIM2 counter modulo registers. The TIM2 overflow interrupt enable
bit, TOIE, enables TIM2 overflow CPU interrupt requests. TOF and TOIE are in the TIM2 status
and control register.
• TIM2 channel flags (CH1F–CH0F) — The CHxF bit is set when an input capture or output compare
occurs on channel x. The channel x interrupt enable bit, CHxIE, enables channel x TIM2 CPU
interrupt requests. CHxF and CHxIE are in the TIM2 channel x status and control register.
14.3.2.7 Serial Peripheral Interface (SPI)
SPI CPU interrupt sources:
• SPI receiver full bit (SPRF) — The SPRF bit is set every time a byte transfers from the shift register
to the receive data register. The SPI receiver interrupt enable bit, SPRIE, enables SPRF CPU
interrupt requests. SPRF is in the SPI status and control register and SPRIE is in the SPI control
register.
• SPI transmitter empty (SPTE) — The SPTE bit is set every time a byte transfers from the transmit
data register to the shift register. The SPI transmit interrupt enable bit, SPTIE, enables SPTE CPU
interrupt requests. SPTE is in the SPI status and control register and SPTIE is in the SPI control
register.
• Mode fault bit (MODF) — The MODF bit is set in a slave SPI if the SS pin goes high during a
transmission with the mode fault enable bit (MODFEN) set. In a master SPI, the MODF bit is set if
the SS pin goes low at any time with the MODFEN bit set. The error interrupt enable bit, ERRIE,
enables MODF CPU interrupt requests. MODF, MODFEN, and ERRIE are in the SPI status and
control register.
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 1
178
Freescale Semiconductor