MC68HC908GZ16 Datasheet, PDF (175/314 Pages) Motorola, Inc – Microcontrollers

Interrupts
After every instruction, the CPU checks all pending interrupts if the I bit is not set. If more than one
interrupt is pending when an instruction is done, the highest priority interrupt is serviced first. In the
example shown in Figure 14-4, if an interrupt is pending upon exit from the interrupt service routine, the
pending interrupt is serviced before the LDA instruction is executed.
CLI
LDA #$FF
BACKGROUND
ROUTINE
INT1
PSHH
PULH
RTI
INT1 INTERRUPT SERVICE ROUTINE
INT2
PSHH
INT2 INTERRUPT SERVICE ROUTINE
PULH
RTI
Figure 14-4. Interrupt Recognition Example
The LDA opcode is prefetched by both the INT1 and INT2 RTI instructions. However, in the case of the
INT1 RTI prefetch, this is a redundant operation.
NOTE
To maintain compatibility with the M6805 Family, the H register is not
pushed on the stack during interrupt entry. If the interrupt service routine
modifies the H register or uses the indexed addressing mode, save the H
register and then restore it prior to exiting the routine.
See Figure 14-5 for a flowchart depicting interrupt processing.
14.3.2 Sources
The sources in Table 14-1 can generate CPU interrupt requests.
14.3.2.1 Software Interrupt (SWI) Instruction
The software interrupt (SWI) instruction causes a non-maskable interrupt.
NOTE
A software interrupt pushes PC onto the stack. An SWI does not push
PC – 1, as a hardware interrupt does.
14.3.2.2 Break Interrupt
The break module causes the CPU to execute an SWI instruction at a software-programmable break
point.
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 1
Freescale Semiconductor
175