N25Q256A13E1240E Datasheet, PDF (90/91 Pages) Micron Technology – Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase N25Q256A

Rev. I – 01/12
Rev. H – 11/11
Rev. G – 07/11
Rev. F – 07/11
Rev. E – 05/11
Rev. D – 05/11
Rev. C – 11/10
Rev. B – 08/10
Rev. A – 06/10
3V, 256Mb: Multiple I/O Serial Flash Memory
Revision History
• Updated DUAL INPUT/OUTPUT FAST READ - DTR third code and added note 11;
added note 12 to QUAD INPUT/OUTPUT FAST READ - DTR in the Command Set ta-
ble
• Updated V_WI min and max specs in the Power-Up Timing and V_WI Threshold table
• Updated Supported Clock Frequencies – STR in Nonvolatile and Volatile Registers
• Added double transfer rate (DTR) mode information
• Miscellaneous edits, including correction of V-PDFN 8 x 6 package and clarification of
feature set option 7.
• Added W# to logic diagram in Device Description
• Cross-reference update to Status Register Bit Definitions table
• Added dummy clock and quad SPI protocol information to Command Definitions
notes
• Corrected Manufacturer ID values
• Removed extraneous frequency requirement note from READ IDENTIFICATIONS Op-
erations
• Corrected timing diagram notes in READ MEMORY Operations
• Corrected timing diagram notes in PROGRAM Operations
• Changed WIP = 1 to WIP = 0 in Power-Up Timing diagram in Power Up and Power
Down
• Micron rebrand
• Added Reset Enable; Read Extended Address Register, Dual I/O; Reset Enable and Re-
set Memory, Dual I/O; Read Extended Address Register, Quad I/O; Reset Enable and
Reset Memory, Quad I/O
• Added information to clarify 4-Byte Address Mode; added reset information, includ-
ing the Reset Enable figure and new rows the Reset Conditions table
• Initial release
PDF: 09005aef84566603
n25q_256mb_65nm.pdf - Rev. Q 05/13 EN
90
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