N25Q256A13E1240E Datasheet, PDF (33/91 Pages) Micron Technology – Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase N25Q256A

3V, 256Mb: Multiple I/O Serial Flash Memory
READ REGISTER and WRITE REGISTER Operations
DQ[1:0]. For quad SPI protocol, the command code is input on DQ[3:0], and is output
on DQ[3:0]. The operation is terminated by driving S# HIGH at any time during data
output.
The nonvolatile configuration register can be read continuously. After all 16 bits of the
register have been read, a 0 is output. All reserved fields output a value of 1.
READ VOLATILE or ENHANCED VOLATILE CONFIGURATION REGISTER Command
To execute a READ VOLATILE CONFIGURATION REGISTER command or a READ EN-
HANCED VOLATILE CONFIGURATION REGISTER command, S# is driven LOW. For ex-
tended SPI protocol, the command code is input on DQ0, and output on DQ1. For dual
SPI protocol, the command code is input on DQ[1:0], and output on DQ[1:0]. For quad
SPI protocol, the command code is input on DQ[3:0], and is output on DQ[3:0]. The op-
eration is terminated by driving S# HIGH at any time during data output.
When the register is read continuously, the same byte is output repeatedly.
READ EXTENDED ADDRESS REGISTER Command
To initiate a READ EXTENDED ADDRESS REGISTER command, S# is driven LOW. For
extended SPI protocol, the command code is input on DQ0, and output on DQ1. For
dual SPI protocol, the command code is input on DQ[1:0], and output on DQ[1:0]. For
quad SPI protocol, the command code is input on DQ[3:0], and is output on DQ[3:0].
The operation is terminated by driving S# HIGH at any time during data output.
When the register is read continuously, the same byte is output repeatedly.
WRITE STATUS REGISTER Command
To issue a WRITE STATUS REGISTER command, the WRITE ENABLE command must be
executed to set the write enable latch bit to 1. S# is driven LOW and held LOW until the
eighth bit of the last data byte has been latched in, after which it must be driven HIGH.
For extended SPI protocol, the command code is input on DQ0, followed by the data
bytes. For dual SPI protocol, the command code is input on DQ[1:0], followed by the da-
ta bytes. For quad SPI protocol, the command code is input on DQ[3:0], followed by the
data bytes. When S# is driven HIGH, the operation, which is self-timed, is initiated; its
duration is ^tW.
This command is used to write new values to status register bits 7:2, enabling software
data protection. The status register can also be combined with the W#/V_PP signal to
provide hardware data protection. The WRITE STATUS REGISTER command has no ef-
fect on status register bits 1:0.
When the operation is in progress, the write in progress bit is set to 1. The write enable
latch bit is cleared to 0, whether the operation is successful or not. The status register
and flag status register can be polled for the operation status. When the operation com-
pletes, the write in progress bit is cleared to 0, whether the operation is successful or
not. If S# is not driven HIGH, the command is not executed, flag status register error
bits are not set, and the write enable latch remains set to 1.
PDF: 09005aef84566603
n25q_256mb_65nm.pdf - Rev. Q 05/13 EN
33
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