N25Q256A13E1240E Datasheet, PDF (25/91 Pages) Micron Technology – Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase N25Q256A

3V, 256Mb: Multiple I/O Serial Flash Memory
Nonvolatile and Volatile Registers
Extended Address Register
For devices whose A[MAX:MIN] equals A[23:0], the N25 family includes an extended ad-
dress register that provides a fourth address byte A[31:24], enabling access to memory
beyond 128Mb. Extended address register bit 0 is used to select the upper 128Mb seg-
ment or the lower 128Mb segment of the memory array.
Figure 9: Upper and Lower 128Mb Memory Array Segments
Upper 128Mb
Bottom 128Mb
01FFFFFFh
00FFFFFFh
EAR<0> = A<24> = 1
01000000h
00000000h
EAR<0> = A<24> = 0
The PROGRAM and ERASE operations act upon the 128Mb segment selected in the ex-
tended address register.
The BULK ERASE operation erases the entire device.
The READ operation begins reading in the selected 128Mb segment, but is not bound
by it. In a continuous READ, when the last byte of the segment is read, the next byte out-
put is the first byte of the other segment as the operation wraps to 0000000h; Therefore,
a download of the whole array is possible with one READ operation. The value of the
extended address register does not change when a READ operation crosses the selected
128Mb boundary.
Table 15: Extended Address Register Bit Definitions
Note 1 applies to entire table
Bit Name
7 A[31:25]
6
5
4
3
2
1
0 A[24]
Settings
0 = Reserved
Description
–
0 = Lower 128Mb segment
(default)
1 = Upper 128Mb segment
Enables 128Mb segmentation selection.
The default setting for this bit is determined by the non-
volatile configuration register bit 1. However, this set-
ting can be changed with the WRITE EXTENDED AD-
DRESS REGISTER command.
Note: 1. The extended address register is for an application that supports only 3-byte addressing.
It extends the device's first three address bytes A[23:0] to a fourth address byte A[31:24]
PDF: 09005aef84566603
n25q_256mb_65nm.pdf - Rev. Q 05/13 EN
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