N25Q256A13E1240E Datasheet, PDF (4/91 Pages) Micron Technology – Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase N25Q256A

3V, 256Mb: Multiple I/O Serial Flash Memory
Features
List of Figures
Figure 1: Logic Diagram ................................................................................................................................... 7
Figure 2: 8-Lead, VDFPN8 – MLP8 (Top View) .................................................................................................. 8
Figure 3: 16-Lead, Plastic Small Outline – SO16 (Top View) ............................................................................... 8
Figure 4: 24-Ball TBGA (Balls Down) ................................................................................................................ 9
Figure 5: Block Diagram ................................................................................................................................ 12
Figure 6: Bus Master and Memory Devices on the SPI Bus ............................................................................... 18
Figure 7: SPI Modes ....................................................................................................................................... 18
Figure 8: Internal Configuration Register ........................................................................................................ 20
Figure 9: Upper and Lower 128Mb Memory Array Segments ........................................................................... 25
Figure 10: READ REGISTER Command .......................................................................................................... 32
Figure 11: WRITE REGISTER Command ......................................................................................................... 34
Figure 12: READ LOCK REGISTER Command ................................................................................................. 36
Figure 13: WRITE LOCK REGISTER Command ............................................................................................... 37
Figure 14: READ ID and MULTIPLE I/O Read ID Commands .......................................................................... 39
Figure 15: READ Command ........................................................................................................................... 46
Figure 16: FAST READ Command ................................................................................................................... 46
Figure 17: DUAL OUTPUT FAST READ Command – STR ................................................................................. 47
Figure 18: DUAL INPUT/OUTPUT FAST READ Command – STR ..................................................................... 47
Figure 19: QUAD OUTPUT FAST READ Command – STR ................................................................................ 48
Figure 20: QUAD INPUT/OUTPUT FAST READ Command – STR .................................................................... 48
Figure 21: FAST READ Command – DTR ......................................................................................................... 49
Figure 22: DUAL OUTPUT FAST READ Command – DTR ................................................................................ 50
Figure 23: DUAL INPUT/OUTPUT FAST READ Command – DTR .................................................................... 50
Figure 24: QUAD OUTPUT FAST READ Command – DTR ............................................................................... 51
Figure 25: QUAD INPUT/OUTPUT FAST READ Command – DTR ................................................................... 51
Figure 26: PAGE PROGRAM Command .......................................................................................................... 53
Figure 27: DUAL INPUT FAST PROGRAM Command ...................................................................................... 54
Figure 28: EXTENDED DUAL INPUT FAST PROGRAM Command ................................................................... 54
Figure 29: QUAD INPUT FAST PROGRAM Command ..................................................................................... 55
Figure 30: EXTENDED QUAD INPUT FAST PROGRAM Command ................................................................... 56
Figure 31: WRITE ENABLE and WRITE DISABLE Command Sequence ............................................................ 58
Figure 32: SUBSECTOR and SECTOR ERASE Command .................................................................................. 60
Figure 33: BULK ERASE Command ................................................................................................................ 61
Figure 34: RESET ENABLE and RESET MEMORY Command ........................................................................... 64
Figure 35: READ OTP Command .................................................................................................................... 65
Figure 36: PROGRAM OTP Command ............................................................................................................ 67
Figure 37: XIP Mode Directly After Power-On .................................................................................................. 70
Figure 38: Power-Up Timing .......................................................................................................................... 72
Figure 39: Reset AC Timing During PROGRAM or ERASE Cycle ........................................................................ 75
Figure 40: Reset Enable ................................................................................................................................. 75
Figure 41: Serial Input Timing ........................................................................................................................ 75
Figure 42: Write Protect Setup and Hold During WRITE STATUS REGISTER Operation (SRWD = 1) ................... 76
Figure 43: Hold Timing .................................................................................................................................. 77
Figure 44: Output Timing .............................................................................................................................. 78
Figure 45: V_PPH Timing .................................................................................................................................. 78
Figure 46: AC Timing Input/Output Reference Levels ...................................................................................... 80
Figure 47: V-PDFN-8/8mm x 6mm ................................................................................................................. 84
Figure 48: SOP2-16/300 mils .......................................................................................................................... 85
Figure 49: T-PBGA-24b05/6mm x 8mm .......................................................................................................... 86
PDF: 09005aef84566603
n25q_256mb_65nm.pdf - Rev. Q 05/13 EN
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