N25Q256A13E1240E Datasheet, PDF (39/91 Pages) Micron Technology – Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase N25Q256A

3V, 256Mb: Multiple I/O Serial Flash Memory
READ IDENTIFICATION Operations
Figure 14: READ ID and MULTIPLE I/O Read ID Commands
Extended
C
DQ0
DQ1
Dual
C
DQ[1:0]
Quad
C
DQ[3:0]
0
7
8
15
16
31
32
Command
MSB
High-Z
0
LSB
D_OUT
MSB
LSB
D_OUT
D_OUT
MSB
LSB
D_OUT
D_OUT
MSB
LSB
D_OUT
Manufacturer
Device
UID
identification
identification
3
4
7
8
15
Command
MSB
LSB
D_OUT
MSB
LSB
D_OUT
D_OUT
MSB
LSB
D_OUT
Manufacturer
identification
Device
identification
0
1
2
3
4
7
Command
MSB
LSB
D_OUT
MSB
LSB
D_OUT
D_OUT
MSB
LSB
D_OUT
Manufacturer
identification
Device
identification
Don’t Care
Note: 1. The READ ID command is represented by the extended SPI protocol timing shown first.
The MULTIPLE I/O READ ID command is represented by the dual and quad SPI protocols
are shown below extended SPI protocol.
READ SERIAL FLASH DISCOVERY PARAMETER Command
To execute READ SERIAL FLASH DISCOVERY PARAMETER command, S# is driven
LOW. The command code is input on DQ0, followed by three address bytes and eight
dummy clock cycles (address is always 3 bytes, even for 4-byte address mode). The de-
vice outputs the information starting from the specified address. When the 2048-byte
boundary is reached, the data output wraps to address 0 of the serial Flash discovery
parameter table. The operation is terminated by driving S# HIGH at any time during da-
ta output.
The operation always executes in continuous mode so the read burst wrap setting in the
volatile configuration register does not apply.
Note: Data to be stored in the serial Flash discovery parameter area is still in the defini-
tion phase.
PDF: 09005aef84566603
n25q_256mb_65nm.pdf - Rev. Q 05/13 EN
39
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