MT41J64M16JT-125G Datasheet, PDF (87/214 Pages) Micron Technology – DDR3 SDRAM MT41J256M4 – 32 Meg x 4 x 8 banks MT41J128M8 – 16 Meg x 8 x 8 banks MT41J64M16 – 8 Meg x 16 x 8 banks

1Gb: x4, x8, x16 DDR3 SDRAM
Electrical Characteristics and AC Operating Conditions
20. The setup and hold times are listed converting the base specification values (to which
derating tables apply) to V_REF when the slew rate is 1 V/ns. These values, with a slew rate
of 1 V/ns, are for reference only.
21. When the device is operated with input clock jitter, this parameter needs to be derated
by the actual ^tJITper (larger of ^tJITper (MIN) or ^tJITper (MAX) of the input clock (output
deratings are relative to the SDRAM input clock).
22. Single-ended signal parameter.
23. The DRAM output timing is aligned to the nominal or average clock. Most output pa-
rameters must be derated by the actual jitter error when input clock jitter is present,
even when within specification. This results in each parameter becoming larger. The fol-
lowing parameters are required to be derated by subtracting ^tERR10per (MAX): ^tDQSCK
(MIN), ^tLZDQS (MIN), ^tLZDQ (MIN), and ^tAON (MIN). The following parameters are re-
quired to be derated by subtracting ^tERR10per (MIN): ^tDQSCK (MAX), ^tHZ (MAX), ^tLZDQS
(MAX), ^tLZDQ MAX, and ^tAON (MAX). The parameter ^tRPRE (MIN) is derated by subtract-
ing ^tJITper (MAX), while ^tRPRE (MAX) is derated by subtracting ^tJITper (MIN).
24. The maximum preamble is bound by ^tLZDQS (MAX).
25. These parameters are measured from a data strobe signal (DQS, DQS#) crossing to its re-
spective clock signal (CK, CK#) crossing. The specification values are not affected by the
amount of clock jitter applied, as these are relative to the clock signal crossing. These
parameters should be met whether clock jitter is present.
26. The ^tDQSCK (DLL_DIS) parameter begins CL + AL - 1 cycles after the READ command.
27. The maximum postamble is bound by ^tHZDQS (MAX).
28. Commands requiring a locked DLL are: READ (and RDAP) and synchronous ODT com-
mands. In addition, after any change of latency ^tXPDLL, timing must be met.
29. ^tIS (base) and ^tIH (base) values are for a single-ended 1 V/ns control/command/address
slew rate and 2 V/ns CK, CK# differential slew rate.
30. These parameters are measured from a command/address signal transition edge to its
respective clock (CK, CK#) signal crossing. The specification values are not affected by
the amount of clock jitter applied as the setup and hold times are relative to the clock
signal crossing that latches the command/address. These parameters should be met
whether clock jitter is present.
31. For these parameters, the DDR3 SDRAM device supports ^tnPARAM (nCK) = RU(^tPARAM
[ns]/^tCK[AVG] [ns]), assuming all input clock jitter specifications are satisfied. For exam-
ple, the device will support ^tnRP (nCK) = RU(^tRP/^tCK[AVG]) if all input clock jitter specifi-
cations are met. This means that for DDR3-800 6-6-6, of which ^tRP = 5ns, the device will
support ^tnRP = RU(^tRP/^tCK[AVG]) = 6 as long as the input clock jitter specifications are
met. That is, the PRECHARGE command at T0 and the ACTIVATE command at T0 + 6 are
valid even if six clocks are less than 15ns due to input clock jitter.
32. During READs and WRITEs with auto precharge, the DDR3 SDRAM will hold off the in-
ternal PRECHARGE command until ^tRAS (MIN) has been satisfied.
33. When operating in DLL disable mode, the greater of 4CK or 15ns is satisfied for ^tWR.
34. The start of the write recovery time is defined as follows:
• For BL8 (fixed by MRS or OTF): Rising clock edge four clock cycles after WL
• For BC4 (OTF): Rising clock edge four clock cycles after WL
• For BC4 (fixed by MRS): Rising clock edge two clock cycles after WL
35. RESET# should be LOW as soon as power starts to ramp to ensure the outputs are in
High-Z. Until RESET# is LOW, the outputs are at risk of driving and could result in exces-
sive current, depending on bus activity.
36. The refresh period is 64ms when T_C is less than or equal to 85°C. This equates to an aver-
age refresh rate of 7.8125μs. However, nine REFRESH commands should be asserted at
least once every 70.3μs. When T_C is greater than 85°C, the refresh period is 32ms.
37. Although CKE is allowed to be registered LOW after a REFRESH command when
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
87
Micron Technology, Inc. reserves the right to change products or specifications without notice.
‹ 2006 Micron Technology, Inc. All rights reserved.