MT41J64M16JT-125G Datasheet, PDF (168/214 Pages) Micron Technology – DDR3 SDRAM MT41J256M4 – 32 Meg x 4 x 8 banks MT41J128M8 – 16 Meg x 8 x 8 banks MT41J64M16 – 8 Meg x 16 x 8 banks

Figure 80: Method for Calculating ^tLZ and ^tHZ
1Gb: x4, x8, x16 DDR3 SDRAM
READ Operation
V_OH - xmV
V_TT + 2xmV
t_HZDQS, t_HZDQ
V_OH - 2xmV
V_TT + xmV
t_LZDQS, t_LZDQ
T2
T1
V_OL + 2xmV
V_OL + xmV
V_TT - xmV
V_TT - 2xmV
T1
T2
t_HZDQS, t_{HZDQ end point = 2 × T1 - T2}
t_LZDQS, t_{LZDQ begin point = 2 × T1 - T2}
Notes:
1. Within a burst, the rising strobe edge is not necessarily fixed at ^tDQSCK (MIN) or ^tDQSCK
(MAX). Instead, the rising strobe edge can vary between ^tDQSCK (MIN) and ^tDQSCK
(MAX).
2. The DQS HIGH pulse width is defined by ^tQSH, and the DQS LOW pulse width is defined
by ^tQSL. Likewise, ^tLZDQS (MIN) and ^tHZDQS (MIN) are not tied to ^tDQSCK (MIN) (early
strobe case), and ^tLZDQS (MAX) and ^tHZDQS (MAX) are not tied to ^tDQSCK (MAX) (late
strobe case); however, they tend to track one another.
3. The minimum pulse width of the READ preamble is defined by ^tRPRE (MIN). The mini-
mum pulse width of the READ postamble is defined by ^tRPST (MIN).
Figure 81: ^tRPRE Timing
CK
CK#
t_A
DQS
Single-ended signal provided
as background information
t_C
DQS#
Single-ended signal provided
as background information
V_TT
t_B
V_TT
t_D
V_TT
T1
t_{RPRE begins}
DQS - DQS#
Resulting differential
signal relevant for
t_{RPRE specification}
tRPRE
0V
T2
t_{RPRE ends}
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
168
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