MT41J64M16JT-125G Datasheet, PDF(51/214 Page) Micron Technology – DDR3 SDRAM MT41J256M4 – 32 Meg x 4 x 8 banks MT41J128M8 – 16 Meg x 8 x 8 banks MT41J64M16

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

MT41J64M16JT-125G Datasheet, PDF (51/214 Pages) Micron Technology – DDR3 SDRAM MT41J256M4 – 32 Meg x 4 x 8 banks MT41J128M8 – 16 Meg x 8 x 8 banks MT41J64M16 – 8 Meg x 16 x 8 banks

◁

1Gb: x4, x8, x16 DDR3 SDRAM

Electrical Specifications â DC and AC

Table 27: Differential Input Operating Conditions (CK, CK# and DQS, DQS#)

Parameter/Condition

Symbol

Min

Max

Unit Notes

Differential input voltage logic high - slew

Differential input voltage logic low - slew

Differential input voltage logic high

Differential input voltage logic low

Differential input crossing voltage relative

to VDD/2 for DQS, DQS#; CK, CK#

Differential input crossing voltage relative

to VDD/2 for CK, CK#

Single-ended high level for strobes

Single-ended high level for CK, CK#

Single-ended low level for strobes

Single-ended low level for CK, CK#

VIH,diff

VIL,diff

VIH,diff(AC)

VIL,diff(AC)

VIX

VIX (175)

VSEH

VSEL

200

n/a

2 Ã (VIH(AC) - VREF)

VSS/VSSQ

VREF(DC) - 150

VREF(DC) - 175

VDDQ/2 + 175

VDD/2 + 175

VSSQ

VSS

n/a

â200

VDD/VDDQ

2 Ã (VIL(AC)-VREF)

VREF(DC) + 150

VREF(DC) + 175

VDDQ

VDD

VDDQ/2 - 175

VDD/2 - 175

mV 4, 7

mV 4, 7, 8

Notes:

1. Clock is referenced to VDD and VSS. Data strobe is referenced to VDDQ and VSSQ.

2. Reference is VREFCA(DC) for clock and VREFDQ(DC) for strobe.

3. Differential input slew rate = 2 V/ns

4. Defines slew rate reference points, relative to input crossing voltages.

5. Minimum DC limit is relative to single-ended signals; overshoot specifications are appli-

cable.

6. Maximum DC limit is relative to single-ended signals; undershoot specifications are ap-

plicable.

7. The typical value of VIX(AC) is expected to be about 0.5 Ã VDD of the transmitting device,

and VIX(AC) is expected to track variations in VDD. VIX(AC) indicates the voltage at which

differential input signals must cross.

8. The VIX extended range (Â±175mV) is allowed only for the clock; this VIX extended range

is only allowed when the following conditions are met: The single-ended input signals

are monotonic, have the single-ended swing VSEL, VSEH of at least VDD/2 Â±250mV, and

the differential slew rate of CK, CK# is greater than 3 V/ns.

9. VIX must provide 25mV (single-ended) of the voltages separation.

PDF: 09005aef826aa906

1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

▷