MT41J64M16JT-125G Datasheet, PDF (60/214 Pages) Micron Technology – DDR3 SDRAM MT41J256M4 – 32 Meg x 4 x 8 banks MT41J128M8 – 16 Meg x 8 x 8 banks MT41J64M16 – 8 Meg x 16 x 8 banks

1Gb: x4, x8, x16 DDR3 SDRAM
ODT Characteristics
Figure 24: ODT Timing Reference Load
CK, CK#
DUT
V_REF ^VDDQ/2
DQ, DM
DQS, DQS#
TDQS, TDQS#
R_TT = 25ȍ
V_TT = V_SSQ
Timing reference point
ZQ
RZQ = 240ȍ
V_SSQ
Table 35: ODT Timing Definitions
Symbol
t_AON
t_AOF
t_AONPD
t_AOFPD
t_ADC
Begin Point Definition
End Point Definition
Rising edge of CK - CK# defined by the end Extrapolated point at V_SSQ
point of ODTLon
Rising edge of CK - CK# defined by the end Extrapolated point at V_RTT,nom
point of ODTLoff
Rising edge of CK - CK# with ODT first being Extrapolated point at V_SSQ
registered HIGH
Rising edge of CK - CK# with ODT first being Extrapolated point at V_RTT,nom
registered LOW
Rising edge of CK - CK# defined by the end Extrapolated points at V_RTT(WR) and
point of ODTLcnw, ODTLcwn4, or ODTLcwn8 V_RTT,nom
Figure
Figure 25 (page 61)
Figure 25 (page 61)
Figure 26 (page 61)
Figure 26 (page 61)
Figure 27 (page 62)
Table 36: Reference Settings for ODT Timing Measurements
Measured Parameter
t_AON
t_AOF
t_AONPD
t_AOFPD
t_ADC
R_TT,nom Setting
RZQ/4 (60Ω
RZQ/12 (20Ω
RZQ/4 (60Ω
RZQ/12 (20Ω
RZQ/4 (60Ω
RZQ/12 (20Ω
RZQ/4 (60Ω
RZQ/12 (20Ω
RZQ/12 (20Ω
R_TT(WR) Setting
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
RZQ/2 (120Ω
V_SW1
50mV
100mV
50mV
100mV
50mV
100mV
50mV
100mV
200mV
V_SW2
100mV
200mV
100mV
200mV
100mV
200mV
100mV
200mV
300mV
Note: 1. Assume an RZQ of 240Ω (±1%) and that proper ZQ calibration has been performed at a
stable temperature and voltage (V_DDQ = V_DD, V_SSQ = V_SS).
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
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