MT41J64M16JT-125G Datasheet, PDF (144/214 Pages) Micron Technology – DDR3 SDRAM MT41J256M4 – 32 Meg x 4 x 8 banks MT41J128M8 – 16 Meg x 8 x 8 banks MT41J64M16 – 8 Meg x 16 x 8 banks

1Gb: x4, x8, x16 DDR3 SDRAM
Mode Register 2 (MR2)
t_{CK. The READ or WRITE command is held for the time of the AL before it is released}
internally to the DDR3 SDRAM device. READ latency (RL) is controlled by the sum of
the AL and CAS latency (CL), RL = AL + CL. WRITE latency (WL) is the sum of CAS
WRITE latency and AL, WL = AL + CWL (see Mode Register 2 (MR2) (page 144)). Exam-
ples of READ and WRITE latencies are shown in Figure 56 (page 144) and Figure 58
(page 145).
Figure 56: READ Latency (AL = 5, CL = 6)
BC4
CK#
CK
Command
T0
ACTIVE n
DQS, DQS#
DQ
T1
T2
READ n
NOP
t_{RCD (MIN)}
AL = 5
T6
T11
NOP
NOP
CL = 6
RL = AL + CL = 11
T12
T13
T14
NOP
NOP
NOP
DO
DO
DO
DO
n
n+1
n+2
n+3
Indicates break
in time scale
Transitioning Data
Don’t Care
Mode Register 2 (MR2)
The mode register 2 (MR2) controls additional functions and features not available in
the other mode registers. These additional functions are CAS WRITE latency (CWL), AU-
TO SELF REFRESH (ASR), SELF REFRESH TEMPERATURE (SRT), and DYNAMIC ODT
(R_TT(WR)). These functions are controlled via the bits shown in Figure 57. The MR2 is
programmed via the MRS command and will retain the stored information until it is
programmed again or until the device loses power. Reprogramming the MR2 register
will not alter the contents of the memory array, provided it is performed correctly. The
MR2 register must be loaded when all banks are idle and no data bursts are in progress,
and the controller must wait the specified time ^tMRD and ^tMOD before initiating a sub-
sequent operation.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
144
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