MT41J64M16JT-125G Datasheet, PDF (178/214 Pages) Micron Technology – DDR3 SDRAM MT41J256M4 – 32 Meg x 4 x 8 banks MT41J128M8 – 16 Meg x 8 x 8 banks MT41J64M16 – 8 Meg x 16 x 8 banks

1Gb: x4, x8, x16 DDR3 SDRAM
WRITE Operation
Figure 94: WRITE (BC4 OTF) to PRECHARGE
T0
T1
CK#
CK
Command1
WRITE
NOP
Address3
Bank,
Col n
DQS, DQS#
DQ4
T2
T3
NOP
NOP
WL = 5
T4
T5
T6
T7
NOP
NOP
NOP
NOP
t_WPRE
t_WPST
DI
DI
DI
DI
n
n+1 n+2 n+3
T8
T9
Tn
NOP
NOP
PRE
t_WR2
Valid
Indicates break
in time scale
Transitioning Data
Don’t Care
Notes:
1. NOP commands are shown for ease of illustration; other commands may be valid at
these times.
2. The write recovery time (^tWR) is referenced from the rising clock edge at T9. ^tWR speci-
fies the last burst WRITE cycle until the PRECHARGE command can be issued to the same
bank.
3. The BC4 setting is activated by MR0[1:0] = 01 and A12 = 0 during the WRITE command
at T0.
4. DI n = data-in for column n.
5. BC4 (OTF), WL = 5, RL = 5.
DQ Input Timing
Figure 85 (page 172) shows the strobe-to-clock timing during a WRITE burst. DQS,
DQS# must transition within 0.25^tCK of the clock transitions, as limited by ^tDQSS. All
data and data mask setup and hold timings are measured relative to the DQS, DQS#
crossing, not the clock crossing.
The WRITE preamble and postamble are also shown in Figure 85 (page 172). One clock
prior to data input to the DRAM, DQS must be HIGH and DQS# must be LOW. Then for
a half clock, DQS is driven LOW (DQS# is driven HIGH) during the WRITE preamble,
t_{WPRE. Likewise, DQS must be kept LOW by the controller after the last data is written}
to the DRAM during the WRITE postamble, ^tWPST.
Data setup and hold times are also shown in Figure 85 (page 172). All setup and hold
times are measured from the crossing points of DQS and DQS#. These setup and hold
values pertain to data input and data mask input.
Additionally, the half period of the data input strobe is specified by ^tDQSH and ^tDQSL.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
178
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