MT41J128M16HA-15ED Datasheet, PDF (56/211 Pages) Micron Technology – DDR3 SDRAM MT41J512M4 – 64 Meg x 4 x 8 Banks MT41J256M8 – 32 Meg x 8 x 8 Banks MT41J128M16 – 16 Meg x 16 x 8 Banks

2Gb: x4, x8, x16 DDR3 SDRAM
ODT Characteristics
Table 32: R_TT Effective Impedances (Continued)
MR1
[9, 6, 2]
1, 0, 0
R_TT
Ω
Resistor
R_TT20(PD40)
R_TT20(PU40)
Ω
V_OUT
0.2 × V_DDQ
0.5 × V_DDQ
0.8 × V_DDQ
0.2 × V_DDQ
0.5 × V_DDQ
0.8 × V_DDQ
V_IL(AC) to V_IH(AC)
Min
0.6
0.9
0.9
0.9
0.9
0.6
0.9
Note: 1. Values assume an RZQ of 240Ω r
Nom
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Max
1.1
1.1
1.4
1.4
1.1
1.1
1.6
Unit
RZQ/6
RZQ/6
RZQ/6
RZQ/6
RZQ/6
RZQ/6
RZQ/12
ODT Sensitivity
If either the temperature or voltage changes after I/O calibration, then the tolerance
limits listed in Table 31 (page 54) and Table 32 can be expected to widen according to
Table 33 and Table 34 (page 56).
Table 33: ODT Sensitivity Definition
Symbol
R_TT
Min
Max
Unit
0.9 - dR_TTdT × |DT| - dR_TTdV × |DV|
1.6 + dR_TTdT × |DT| + dR_TTdV × |DV|
RZQ/(2, 4, 6, 8, 12)
Note: 1. ΔT = T - T(@ calibration), ΔV = V_DDQ - V_DDQ(@ calibration) and V_DD = V_DDQ.
Table 34: ODT Temperature and Voltage Sensitivity
Change
Min
Max
Unit
dR_TTdT
dR_TTdV
0
1.5
%/°C
0
0.15
%/mV
Note: 1. ΔT = T - T(@ calibration), ΔV = V_DDQ - V_DDQ(@ calibration) and V_DD = V_DDQ.
ODT Timing Definitions
ODT loading differs from that used in AC timing measurements. The reference load for
ODT timings is shown in Figure 22. Two parameters define when ODT turns on or off
synchronously, two define when ODT turns on or off asynchronously, and another de-
fines when ODT turns on or off dynamically. Table 35 outlines and provides definition
and measurement references settings for each parameter (see Table 36 (page 57)).
ODT turn-on time begins when the output leaves High-Z and ODT resistance begins to
turn on. ODT turn-off time begins when the output leaves Low-Z and ODT resistance
begins to turn off.
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN
56
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