MT41J128M16HA-15ED Datasheet, PDF (191/211 Pages) Micron Technology – DDR3 SDRAM MT41J512M4 – 64 Meg x 4 x 8 Banks MT41J256M8 – 32 Meg x 8 x 8 Banks MT41J128M16 – 16 Meg x 16 x 8 Banks

2Gb: x4, x8, x16 DDR3 SDRAM
On-Die Termination (ODT)
Table 83: Truth Table – ODT (Nominal)
Note 1 applies to the entire table
MR1[9, 6, 2]
ODT Pin
000
0
000
1
000–101
0
000–101
1
110 and 111
X
DRAM Termination State
R_TT,nom disabled, ODT off
R_TT,nom disabled, ODT on
R_TT,nom enabled, ODT off
R_TT,nom enabled, ODT on
R_TT,nom reserved, ODT on or off
DRAM State
Any valid
Any valid except self refresh, read
Any valid
Any valid except self refresh, read
Illegal
Notes
2
3
2
3
Notes:
1. Assumes dynamic ODT is disabled (see Dynamic ODT (page 192) when enabled).
2. ODT is enabled and active during most writes for proper termination, but it is not illegal
for it to be off during writes.
3. ODT must be disabled during reads. The R_TT,nom value is restricted during writes. Dynam-
ic ODT is applicable if enabled.
Nominal ODT resistance R_TT,nom is defined by MR1[9, 6, 2], as shown in Mode Register 1
(MR1) Definition. The R_TT,nom termination value applies to the output pins previously
mentioned. DDR3 SDRAM supports multiple R_TT,nom values based on RZQ/n where n
can be 2, 4, 6, 8, or 12 and RZQ is 240Ω. R_TT,nom termination is allowed any time after the
DRAM is initialized, calibrated, and not performing read access, or when it is not in self
refresh mode.
Write accesses use R_TT,nom if dynamic ODT (R_TT(WR)) is disabled. If R_TT,nom is used dur-
ing writes, only RZQ/2, RZQ/4, and RZQ/6 are allowed (see Table 87 (page 193)). ODT
timings are summarized in Table 84 (page 191), as well as listed in Table 56 (page 76).
Examples of nominal ODT timing are shown in conjunction with the synchronous
mode of operation in Synchronous ODT Mode (page 198).
Table 84: ODT Parameters
Symbol
ODTLon
ODTLoff
t_AONPD
t_AOFPD
ODTH4
ODTH8
t_AON
t_AOF
Description
Begins at
Defined to
Definition for All
DDR3 Speed Bins
ODT synchronous turn-on delay
ODT synchronous turn-off delay
ODT asynchronous turn-on delay
ODT asynchronous turn-off delay
ODT minimum HIGH time after ODT
assertion or write (BC4)
ODT registered HIGH
ODT registered HIGH
ODT registered HIGH
ODT registered HIGH
ODT registered HIGH
or write registration
with ODT HIGH
R_TT(ON) ±^tAON
R_TT(OFF) ±^tAOF
R_TT(ON)
R_TT(OFF)
ODT registered
LOW
CWL + AL - 2
CWL + AL - 2
2–8.5
2–8.5
4^tCK
ODT minimum HIGH time after
write (BL8)
Write registration ODT registered
with ODT HIGH
LOW
6^tCK
ODT turn-on relative to ODTLon
completion
Completion of
ODTLon
R_TT(ON)
See Table 56 (page 76)
ODT turn-off relative to ODTLoff
completion
Completion of
ODTLoff
R_TT(OFF)
0.5^tCK ± 0.2^tCK
Unit
t_CK
t_CK
ns
ns
t_CK
t_CK
ps
t_CK
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