MT41J128M16HA-15ED Datasheet, PDF (149/211 Pages) Micron Technology – DDR3 SDRAM MT41J512M4 – 64 Meg x 4 x 8 Banks MT41J256M8 – 32 Meg x 8 x 8 Banks MT41J128M16 – 16 Meg x 16 x 8 Banks

Figure 60: MPR System Read Calibration with BL8: Fixed Burst Order, Back-to-Back Readout
T0
Ta
Tb
Tc0
Tc1
Tc2
Tc3
Tc4
Tc5
Tc6
Tc7
Tc8
Tc9
Tc10
Td
CK#
CK
Command PREA
MRS
READ¹
READ¹
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
MRS
Valid
t_RP
t_MOD
t_CCD
t_MPRR
t_MOD
Bank address
3
Valid
Valid
3
A[1:0]
A2
0
0²
0²
1
0²
1²
Valid
0
A[9:3]
00
Valid
Valid
00
A10/AP
1
0
Valid
Valid
0
A11
0
Valid
Valid
0
A12/BC#
0
Valid
Valid¹
0
A[15:13]
0
Valid
Valid
0
RL
DQS, DQS#
RL
DQ
Notes: 1. READ with BL8 either by MRS or OTF.
2. Memory controller must drive 0 on A[2:0].
Indicates break
in time scale
Don’t Care