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| MT41J128M16HA-15ED Datasheet, PDF (100/211 Pages) Micron Technology – DDR3 SDRAM MT41J512M4 – 64 Meg x 4 x 8 Banks MT41J256M8 – 32 Meg x 8 x 8 Banks MT41J128M16 – 16 Meg x 16 x 8 Banks | |||
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2Gb: x4, x8, x16 DDR3 SDRAM
Command and Address Setup, Hold, and Derating
Figure 32: Nominal Slew Rate and tVAC for tIS (Command and Address â Clock)
tIS
tIH
tIS
tIH
CK
CK#
DQS#
DQS
VDDQ
tVAC
VIH(AC)min
VIH(DC)min
VREF to AC
region
VREF(DC)
VIL(DC)max
VIL(DC)max
Nominal
slew rate
Nominal
slew rate
VREF to AC
region
tVAC
VSS
ǻTF
ǻTR
Setup slew rate
VREF(DC) - VIL(AC)max
falling signal =
ǻTF
Setup slew rate
VIH(AC)min - VREF(DC)
rising signal =
ǻTR
Note: 1. The clock and the strobe are drawn on different time scales.
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN
100
Micron Technology, Inc. reserves the right to change products or specifications without notice.
 2006 Micron Technology, Inc. All rights reserved.
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