MT41J128M16HA-15ED Datasheet, PDF (185/211 Pages) Micron Technology – DDR3 SDRAM MT41J512M4 – 64 Meg x 4 x 8 Banks MT41J256M8 – 32 Meg x 8 x 8 Banks MT41J128M16 – 16 Meg x 16 x 8 Banks

2Gb: x4, x8, x16 DDR3 SDRAM
Power-Down Mode
Figure 100: Power-Down Entry After WRITE with Auto Precharge (WRAP)
T0
CK#
CK
Command WRAP
CKE
Address Valid
A10
DQS, DQS#
DQ BL8
DQ BC4
T1
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Ta7
Tb0
Tb1
Tb2
Tb3
Tb4
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
t_IS t_CPDED
WL = AL + CWL
WR¹
t_PD
DI
n
DI
n+1
DI
n+2
DI
n+3
DI
n+4
DI
n+5
DI
n+6
DI
n+7
DI DI DI DI
n n+1 n+2 n+3
t_WRAPDEN
Start internal
precharge
Power-down or
self refresh entry²
Indicates break
in time scale
Transitioning Data
Don’t Care
Notes: 1. ^tWR is programmed through MR0[11:9] and represents ^tWRmin (ns)/^tCK rounded up to
the next integer ^tCK.
2. CKE can go LOW 2^tCK earlier if BC4MRS.
Figure 101: REFRESH to Power-Down Entry
CK#
CK
Command
CKE
T0
T1
T2
T3
Ta0
Ta1
Ta2
Tb0
t_CK
t_CH
t_CL
REFRESH
NOP
NOP
t_CPDED
t_IS
t_PD
NOP
NOP
Valid
t_{CKE (MIN)}
t_REFPDEN
t_{RFC (MIN)}1
t_{XP (MIN)}
Indicates break
in time scale
Don’t Care
Note: 1. After CKE goes HIGH during ^tRFC, CKE must remain HIGH until ^tRFC is satisfied.
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN
185
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