MT41J128M16HA-15ED Datasheet, PDF (31/211 Pages) Micron Technology – DDR3 SDRAM MT41J512M4 – 64 Meg x 4 x 8 Banks MT41J256M8 – 32 Meg x 8 x 8 Banks MT41J128M16 – 16 Meg x 16 x 8 Banks

2Gb: x4, x8, x16 DDR3 SDRAM
Electrical Specifications – I_DD Specifications and Conditions
Table 9: I_DD0 Measurement Loop
0
1
2
3
4
nRAS
0
nRC
nRC + 1
nRC + 2
nRC + 3
nRC + 4
nRC + nRAS
1
2 × nRC
2
4 × nRC
3
6 × nRC
4
8 × nRC
5 10 × nRC
6 12 × nRC
7 14 × nRC
ACT
00110000000
–
D
10000000000
–
D
10000000000
–
D#
11110000000
–
D#
11110000000
–
Repeat cycles 1 through 4 until nRAS - 1; truncate if needed
PRE
00100000000
–
Repeat cycles 1 through 4 until nRC - 1; truncate if needed
ACT
001100000F0
–
D
100000000F0
–
D
100000000F0
–
D#
111100000F0
–
D#
111100000F0
–
Repeat cycles nRC + 1 through nRC + 4 until nRC - 1 + nRAS -1; truncate if needed
PRE
001000000F0
–
Repeat cycles nRC + 1 through nRC + 4 until 2 × RC - 1; truncate if needed
Repeat sub-loop 0, use BA[2:0] = 1
Repeat sub-loop 0, use BA[2:0] = 2
Repeat sub-loop 0, use BA[2:0] = 3
Repeat sub-loop 0, use BA[2:0] = 4
Repeat sub-loop 0, use BA[2:0] = 5
Repeat sub-loop 0, use BA[2:0] = 6
Repeat sub-loop 0, use BA[2:0] = 7
Notes: 1. DQ, DQS, DQS# are midlevel.
2. DM is LOW.
3. Only selected bank (single) active.
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN
31
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