MT41J128M16HA-15ED Datasheet, PDF(201/211 Page) Micron Technology – DDR3 SDRAM MT41J512M4 – 64 Meg x 4 x 8 Banks MT41J256M8 – 32 Meg x 8 x 8 Banks MT41J128M16 – 16 Meg x 16 x 8 Banks

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MT41J128M16HA-15ED Datasheet, PDF (201/211 Pages) Micron Technology – DDR3 SDRAM MT41J512M4 – 64 Meg x 4 x 8 Banks MT41J256M8 – 32 Meg x 8 x 8 Banks MT41J128M16 – 16 Meg x 16 x 8 Banks

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2Gb: x4, x8, x16 DDR3 SDRAM

Synchronous ODT Mode

ODT Off During READs

Because the device cannot terminate and drive at the same time, RTT must be disabled

at least one-half clock cycle before the READ preamble by driving the ODT ball LOW (if

either RTT,nom or RTT(WR) is enabled). RTT may not be enabled until the end of the post-

amble, as shown in the following example.

Note: ODT may be disabled earlier and enabled later than shown in Figure 115

(page 202).

PDF: 09005aef826aaadc

2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN

201

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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