MT41J128M16HA-15ED Datasheet, PDF (207/211 Pages) Micron Technology – DDR3 SDRAM MT41J512M4 – 64 Meg x 4 x 8 Banks MT41J256M8 – 32 Meg x 8 x 8 Banks MT41J128M16 – 16 Meg x 16 x 8 Banks

2Gb: x4, x8, x16 DDR3 SDRAM
Asynchronous to Synchronous ODT Mode Transition (Power-
Down Exit)
Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit)
The DRAM’s ODT can exhibit either asynchronous or synchronous behavior during
power-down exit (PDX). This transition period occurs if the DLL is selected to be off
when in precharge power-down mode by setting MR0[12] to 0. Power-down exit begins
t_{ANPD prior to CKE first being registered HIGH, and ends} t_{XPDLL after CKE is first reg-}
istered HIGH. ^tANPD is equal to the greater of ODTLoff + 1^tCK or ODTLon + 1^tCK. The
transition period is ^tANPD + ^tXPDLL.
ODT assertion during power-down exit results in an R_TT change as early as the lesser of
t_{AONPD (MIN) and ODTLon ×} t_{CK +} t_{AON (MIN), or as late as the greater of} t_AONPD
(MAX) and ODTLon × ^tCK + ^tAON (MAX). ODT de-assertion during power-down exit
may result in an R_TT change as early as the lesser of ^tAOFPD (MIN) and ODTLoff × ^tCK +
t_{AOF (MIN), or as late as the greater of} t_{AOFPD (MAX) and ODTLoff ×} t_{CK +} t_{AOF (MAX).}
Table 92 (page 206) summarizes these parameters.
If AL has a large value, the uncertainty of the R_TT state becomes quite large. This is be-
cause ODTLon and ODTLoff are derived from WL, and WL is equal to CWL + AL. Fig-
ure 118 (page 208) shows three different cases:
• ODT C: Asynchronous behavior before ^tANPD.
• ODT B: ODT state changes during the transition period, with ^tAOFPD (MIN) < ODTL-
off × ^tCK + ^tAOF (MIN), and ODTLoff × ^tCK + ^tAOF (MAX) > ^tAOFPD (MAX).
• ODT A: ODT state changes after the transition period with synchronous response.
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN
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