MT40A512M8RH-075EAUT Datasheet, PDF (5/359 Pages) Micron Technology – Automotive DDR4 SDRAM

4Gb: x8, x16 Automotive DDR4 SDRAM
Features
V_REFDQ Range and Levels ........................................................................................................................... 113
V_REFDQ Step Size ........................................................................................................................................ 113
V_REFDQ Increment and Decrement Timing .................................................................................................. 114
V_REFDQ Target Settings ............................................................................................................................... 118
Connectivity Test Mode ................................................................................................................................. 120
Pin Mapping ............................................................................................................................................. 120
Minimum Terms Definition for Logic Equations ......................................................................................... 121
Logic Equations for a x4 Device, When Supported ....................................................................................... 121
Logic Equations for a x8 Device, When Supported ....................................................................................... 122
Logic Equations for a x16 Device ................................................................................................................ 122
CT Input Timing Requirements .................................................................................................................. 122
Excessive Row Activation ............................................................................................................................... 124
Post Package Repair ....................................................................................................................................... 125
Post Package Repair ................................................................................................................................... 125
Hard Post Package Repair .......................................................................................................................... 126
hPPR Row Repair - Entry ........................................................................................................................ 126
hPPR Row Repair – WRA Initiated (REF Commands Allowed) .................................................................. 126
hPPR Row Repair – WR Initiated (REF Commands NOT Allowed) ............................................................. 128
sPPR Row Repair ....................................................................................................................................... 130
hPPR/sPPR Support Identifier .................................................................................................................... 133
ACTIVATE Command .................................................................................................................................... 133
PRECHARGE Command ................................................................................................................................ 134
REFRESH Command ..................................................................................................................................... 135
Temperature-Controlled Refresh Mode .......................................................................................................... 137
TCR Mode – Normal Temperature Range .................................................................................................... 137
TCR Mode – Extended Temperature Range ................................................................................................. 137
Fine Granularity Refresh Mode ....................................................................................................................... 139
Mode Register and Command Truth Table .................................................................................................. 139
t_{REFI and} t_{RFC Parameters ........................................................................................................................ 139}
Changing Refresh Rate ............................................................................................................................... 142
Usage with TCR Mode ................................................................................................................................ 142
Self Refresh Entry and Exit ......................................................................................................................... 142
SELF REFRESH Operation .............................................................................................................................. 144
Self Refresh Abort ...................................................................................................................................... 146
Self Refresh Exit with NOP Command ......................................................................................................... 147
Power-Down Mode ........................................................................................................................................ 149
Power-Down Clarifications – Case 1 ........................................................................................................... 154
Power-Down Entry, Exit Timing with CAL ................................................................................................... 155
ODT Input Buffer Disable Mode for Power-Down ............................................................................................ 157
CRC Write Data Feature ................................................................................................................................. 159
CRC Write Data ......................................................................................................................................... 159
WRITE CRC DATA Operation ...................................................................................................................... 159
DBI_n and CRC Both Enabled .................................................................................................................... 160
DM_n and CRC Both Enabled .................................................................................................................... 160
DM_n and DBI_n Conflict During Writes with CRC Enabled ........................................................................ 160
CRC and Write Preamble Restrictions ......................................................................................................... 160
CRC Simultaneous Operation Restrictions .................................................................................................. 160
CRC Polynomial ........................................................................................................................................ 160
CRC Combinatorial Logic Equations .......................................................................................................... 161
Burst Ordering for BL8 ............................................................................................................................... 162
CRC Data Bit Mapping ............................................................................................................................... 162
CRC Enabled With BC4 .............................................................................................................................. 163
CCMTD-1725822587-10418
4gb_auto_ddr4_sdram_z90b.pdf - Rev. D 01/17 EN
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