MT40A512M8RH-075EAUT Datasheet, PDF (330/359 Pages) Micron Technology – Automotive DDR4 SDRAM

4Gb: x8, x16 Automotive DDR4 SDRAM
Speed Bin Tables
5. If the clock period is less than 0.938ns and greater than or equal to 0.937ns, timing pa-
rameters that are derived off the clock will use 0.938ns as its reference. For example, if
t_{CK (MIN) = 0.938ns and} t_{RP = 14.06ns, then} t_{RP would require 15nCKs (14.06ns/}
0.938ns), but if ^tCK (MIN) = 0.937ns and ^tRP = 14.06ns, then ^tRP would still require
15nCKs (14.06ns/ 0.938ns) and not 16nCKs (14.06ns/ 0.937ns).
6. When calculating ^tRC and ^tRP in clocks, values may not be used in a combination that
would violate ^tRAS.
Table 154: DDR4-2666 Speed Bins and Operating Conditions
DDR4-2666 Speed Bin
CL-nRCD-nRP
Parameter
Internal READ command to first data
Internal READ command to first data
with read DBI enabled
Symbol
t_AA
t_{AA_DBI}
ACTIVATE to internal READ or WRITE
delay time
t_RCD
PRECHARGE command period
t_RP
ACTIVATE-to-PRECHARGE command
period
t_RAS
ACTIVATE-to-ACTIVATE or REFRESH
t_RC7
command period
READ: READ: DBI WRITE
nonDBI
Symbol
CL = 9 CL = 11
CWL = 9
t_CK4
CL = 10 CL = 12
CWL = 9
t_CK4
CL = 10 CL = 12
CWL = 9, 11
t_CK4
CL = 11 CL = 13
CWL = 9, 11
t_CK4
CL = 12 CL = 14
CWL = 9, 11
t_CK4
CL = 12 CL = 14
CWL = 10, 12 ^tCK⁴
CL = 13 CL = 15
CWL = 10, 12 ^tCK⁴
CL = 14 CL = 16
CWL = 10, 12 ^tCK⁴
CL = 14 CL =17
CWL = 11, 14 ^tCK⁴
CL = 15 CL = 18
CWL = 11, 14 ^tCK⁴
CL = 16 CL = 19
CWL = 11, 14 ^tCK⁴
CL = 15 CL = 18
CWL = 12, 16 ^tCK⁴
CL = 16 CL = 19
CWL = 12, 16 ^tCK⁴
CL = 17 CL = 20
CWL = 12, 16 ^tCK⁴
CL = 18 CL = 21
CWL = 12, 16 ^tCK⁴
CL = 17 CL = 20
CWL = 14, 18 ^tCK⁴
CL = 18 CL = 21
CWL = 14, 18 ^tCK⁴
CL = 19 CL = 22
CWL = 14, 18 ^tCK⁴
-075F
17-17-17
Min
Max
12.75
19.00
t_AA
(MIN) +
3nCK
t_AA
(MAX) +
3nCK
12.75
–
12.75
32
–
9 × ^tREFI
t_{RAS +}
t_RP
Min
–
Max
1.5
1.9
1.5
1.9
Reserved
1.25
<1.5
1.25
<1.5
Reserved
1.071 <1.25
1.071 <1.25
Reserved
0.937⁶ <1.071
0.937 <1.071
Reserved
0.833 <0.937
0.833 <0.937
0.833 <0.937
0.750 <0.833
0.750 <0.833
0.750 <0.833
-075E
18-18-18
Min
Max
13.5
19.00
t_AA
(MIN) +
3nCK
t_AA
(MAX) +
3nCK
13.5
–
13.5
32
–
9 × ^tREFI
t_{RAS +}
t_RP
Min
–
Max
1.5
1.9
1.5
1.9
Reserved
1.25
<1.5
1.25
<1.5
Reserved
1.071 <1.25
1.071 <1.25
Reserved
0.937 <1.071
0.937 <1.071
Reserved
Reserved
0.833 <0.937
0.833 <0.937
Reserved
0.750 <0.833
0.750 <0.833
-075
19-19-19
Min
Max
14.25⁵ 19.00
t_AA
(MIN) +
3nCK
t_AA
(MAX) +
3nCK
14.25⁵
–
Unit
ns
ns
ns
14.25⁵
–
ns
32
9 × ^tREFI ns
t_{RAS +}
t_RP
Min
–
ns
Max Unit
Reserved
ns
1.5
1.9
ns
Reserved
ns
1.25
<1.5
ns
1.25
<1.5
ns
Reserved
ns
1.071 <1.25 ns
1.071 <1.25 ns
Reserved
ns
0.937 <1.071 ns
0.937 <1.071 ns
Reserved
ns
Reserved
ns
0.833 <0.937 ns
0.833 <0.937 ns
Reserved
ns
Reserved
ns
0.750 <0.833 ns
CCMTD-1725822587-10418
4gb_auto_ddr4_sdram_z90b.pdf - Rev. D 01/17 EN
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