MT40A512M8RH-075EAUT Datasheet, PDF (25/359 Pages) Micron Technology – Automotive DDR4 SDRAM

4Gb: x8, x16 Automotive DDR4 SDRAM
Ball Descriptions
Table 3: Ball Descriptions (Continued)
Symbol
DQ
DBI_n,
UDBI_n,
LDBI_n
DQS_t,
DQS_c,
DQSU_t,
DQSU_c,
DQSL_t,
DQSL_c
ALERT_n
TDQS_t,
TDQS_c
V_DD
V_DDQ
V_PP
V_REFCA
V_SS
V_SSQ
ZQ
RFU
NC
NF
Type
I/O
I/O
I/O
Output
Output
Supply
Supply
Supply
Supply
Supply
Supply
Reference
–
–
–
Description
Data input/output: Bidirectional data bus. DQ represents DQ[3:0], DQ[7:0], and
DQ[15:0] for the x4, x8, and x16 configurations, respectively. If write CRC is enabled
via mode register, the write CRC code is added at the end of data burst. Any one or
all of DQ0, DQ1, DQ2, and DQ3 may be used to monitor the internal V_REF level during
test via mode register setting MR[4] A[4] = HIGH, training times change when ena-
bled. During this mode, the R_TT value should be set to High-Z. This measurement is
for verification purposes and is NOT an external voltage supply pin.
DBI input/output: Data bus inversion. DBI_n is an input/output signal used for data
bus inversion in the x8 configuration. UDBI_n and LDBI_n are used in the x16 configu-
ration; UDBI_n is associated with DQ[15:8], and LDBI_n is associated with DQ[7:0]. The
DBI feature is not supported on the x4 configuration. DBI can be configured for both
READ (output) and WRITE (input) operations depending on the mode register set-
tings. The DM, DBI, and TDQS functions are enabled by mode register settings. See
the Data Bus Inversion section.
Data strobe: Output with READ data, input with WRITE data. Edge-aligned with
READ data, centered-aligned with WRITE data. For the x16, DQSL corresponds to the
data on DQ[7:0]; DQSU corresponds to the data on DQ[15:8]. For the x4 and x8 con-
figurations, DQS corresponds to the data on DQ[3:0] and DQ[7:0], respectively. DDR4
SDRAM supports a differential data strobe only and does not support a single-ended
data strobe.
Alert output: This signal allows the DRAM to indicate to the system's memory con-
troller that a specific alert or event has occurred. Alerts will include the command/
address parity error and the CRC data error when either of these functions is enabled
in the mode register.
Termination data strobe: TDQS_t and TDQS_c are used by x8 DRAMs only. When
enabled via the mode register, the DRAM will enable the same R_TT termination resist-
ance on TDQS_t and TDQS_c that is applied to DQS_t and DQS_c. When the TDQS
function is disabled via the mode register, the DM/TDQS_t pin will provide the DATA
MASK (DM) function, and the TDQS_c pin is not used. The TDQS function must be dis-
abled in the mode register for both the x4 and x16 configurations. The DM function
is supported only in x8 and x16 configurations.
Power supply: 1.2V ±0.060V.
DQ power supply: 1.2V ±0.060V.
DRAM activating power supply: 2.5V –0.125V/+0.250V.
Reference voltage for control, command, and address pins.
Ground.
DQ ground.
Reference ball for ZQ calibration: This ball is tied to an external 240Ω resistor
(RZQ), which is tied to V_SSQ.
Reserved for future use.
No connect: No internal electrical connection is present.
No function: May have internal connection present but has no function.
CCMTD-1725822587-10418
4gb_auto_ddr4_sdram_z90b.pdf - Rev. D 01/17 EN
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