MT40A512M8RH-075EAUT Datasheet, PDF (195/359 Pages) Micron Technology – Automotive DDR4 SDRAM

4Gb: x8, x16 Automotive DDR4 SDRAM
READ Operation
Figure 130: READ (BC4) to READ (BC4) with 1^tCK Preamble in Different Bank Group
T0
T1
T2
T3
T4
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CK_c
CK_t
Command READ
Bank Group _BGa
Address
Address
Bank
Col n
DQS_t,
DQS_c
DQ
DES
DES
DES
READ
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
t_{CCD_S = 4}
BGb
Bank
Col b
t_RPRE
t_RPST
t_RPRE
t_RPST
RL = 11
DO DO DO DO
n n+1 n+2 n+3
RL = 11
DO DO DO DO
b b+1 b+2 b+3
Time Break
Transitioning Data
Don’t Care
Notes:
1. BL8, AL = 0, CL = 11, Preamble = 1^tCK.
2. DO n (or b) = data-out from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by either MR0[1:0] = 10 or MR0[1:0] = 01 and A12 = 0 during READ
commands at T0 and T4.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.
Figure 131: READ (BC4) to READ (BC4) with 2^tCK Preamble in Different Bank Group
T0
T1
T2
T3
T4
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CK_c
CK_t
Command READ
Bank Group _BGa
Address
Address
Bank
Col n
DQS_t,
DQS_c
DQ
DES
DES
DES
READ
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
t_{CCD_S = 4}
BGb
Bank
Col b
t_RPRE
t_RPRE
t_RPST
RL = 11
DO DO DO DO
n n+1 n+2 n+3
RL = 11
DO DO DO DO
b b+1 b+2 b+3
Time Break
Transitioning Data
Don’t Care
Notes:
1. BL8, AL = 0, CL = 11, Preamble = 2^tCK.
2. DO n (or b) = data-out from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by either MR0[1:0] = 10 or MR0[1:0] = 01 and A12 = 0 during READ
commands at T0 and T4.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.
CCMTD-1725822587-10418
4gb_auto_ddr4_sdram_z90b.pdf - Rev. D 01/17 EN
195
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