MT40A512M8RH-075EAUT Datasheet, PDF (169/359 Pages) Micron Technology – Automotive DDR4 SDRAM

CRC Write Data Flow Diagram
Figure 103: CA Parity Flow Diagram
DRAM write
process start
Capture data
MR2 12 enable CRC
MR5 3 set CRC error clear to 0
MR5 10 enable/disable DM
MR3[10:9] WCL if DM enabled
CRC
Yes
enabled
No
Transfer Data
Internally
Yes
CA error
No
Persistent _Yes
mode
enabled
No
Transfer data
internally
DRAM
CRC same as ^No
controller
CRC
Yes
Transfer data
internally
DRAM
CRC same as
controller
CRC
Yes
No
ALERT_n LOW
6 to 10 CKs
ALERT_n HIGH
MR5[3] = 0 ^Yes
at WRITE
No
MR5[A3] and
PAGE1 MPR3[7]
remain set to 1
Set error flag
MR5[A3] 1
Set error status
PAGE1 MPR3[7] 1
ALERT_n LOW
6 to 10 CKs
ALERT_n HIGH
MR5[3] = 0 ^Yes
at WRITE
No
MR5[A3] and
PAGE1 MPR3[7]
remain set to 1
Set error flag
MR5[A3] 1
Set error status
PAGE1 MPR3[7] 1
WRITE burst
completed
WRITE burst
completed
WRITE burst
completed
WRITE burst
completed
Bad data written
MR5 3 reset to 0 if desired
WRITE burst
completed
WRITE burst
rejected
Bad data not written
MR5 3 reset to 0 if desired