MT40A512M8RH-075EAUT Datasheet, PDF (266/359 Pages) Micron Technology – Automotive DDR4 SDRAM

4Gb: x8, x16 Automotive DDR4 SDRAM
Electrical Characteristics – AC and DC Single-Ended Input
Measurement Levels
Table 91: DQ Input Receiver Specifications (Continued)
Note 1 applies to the entire table
DDR4-1600,
1866, 2133
Parameter
Symbol Min Max
DQ input pulse
width
TdiPW 0.58 –
DQS-to-DQ Rx
mask offset
t_{DQS2D –0.17 0.17}
Q
DQ-to-DQ Rx mask ^tDQ2DQ –
0.1
offset
Input slew rate srr1, srf1 1
9
over V_diVW if ^tCK ≥
0.925ns
Input slew rate srr1, srf1 –
–
over V_diVW if
0.935ns > ^tCK ≥
0.625ns
Rising input slew
srr2 0.2 × 9
rate over 1/2
srr1
V_IHL(AC)
Falling input slew srf2 0.2 × 9
rate over 1/2
srf1
V_IHL(AC)
DDR4-2400
Min Max
0.58 –
–0.17 0.17
–
0.1
1
9
1.25 9
0.2 × 9
srr1
0.2 × 9
srf1
DDR4-2666
Min Max
0.58 –
–0.19 0.19
– 0.105
1
9
1.25 9
0.2 × 9
srr1
0.2 × 9
srf1
DDR4-2933
Min Max
0.58 –
–0.22 0.22
– 0.115
1
9
1.25 9
0.2 × 9
srr1
0.2 × 9
srf1
DDR4-3200
Min Max
0.58 –
Not
Unit es
UI 6
–0.22 0.22 UI 7
– 0.125 UI 8
1
9 V/ns 9
1.25 9 V/ns 9
0.2 ×
srr1
9 V/ns 10
0.2 ×
srf1
9 V/ns 10
Notes: 1. All Rx mask specifications must be satisfied for each UI. For example, if the minimum in-
put pulse width is violated when satisfying TdiVW (MIN), V_diVW,max, and minimum slew
rate limits, then either TdiVW (MIN) or minimum slew rates would have to be increased
to the point where the minimum input pulse width would no longer be violated.
2. Data Rx mask voltage and timing total input valid window where V_diVW is centered
around V_{CENTDQ,midpoint} after V_REFDQ training is completed. The data Rx mask is applied
per bit and should include voltage and temperature drift terms. The input buffer design
specification is to achieve at least a BER =1^{e- 16} when the Rx mask is not violated.
3. Defined over the DQ internal V_REF range 1.
4. Overshoot and undershoot specifications apply.
5. DQ input pulse signal swing into the receiver must meet or exceed V_IHL(AC)min. V_IHL(AC)min
is to be achieved on an UI basis when a rising and falling edge occur in the same UI (a
valid TdiPW).
6. DQ minimum input pulse width defined at the V_{CENTDQ,midpoint}.
7. DQS-to-DQ Rx mask offset is skew between DQS and DQ within a nibble (x4) or word
(x8, x16 [for x16, the upper and lower bytes are treated as separate x8s]) at the SDRAM
balls over process, voltage, and temperature.
8. DQ-to-DQ Rx mask offset is skew between DQs within a nibble (x4) or word (x8, x16) at
the SDRAM balls for a given component over process, voltage, and temperature.
9. Input slew rate over V_diVW mask centered at V_{CENTDQ,midpoint}. Slowest DQ slew rate to
fastest DQ slew rate per transition edge must be within 1.7V/ns of each other.
10. Input slew rate between V_diVW mask edge and V_IHL(AC)min points.
CCMTD-1725822587-10418
4gb_auto_ddr4_sdram_z90b.pdf - Rev. D 01/17 EN
266
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