MT40A512M8RH-075EAUT Datasheet, PDF (19/359 Pages) Micron Technology – Automotive DDR4 SDRAM

4Gb: x8, x16 Automotive DDR4 SDRAM
General Notes and Description
• The terms "DQS" and "CK" found throughout the data sheet are to be interpreted as
DQS_t and DQS_c, and CK_t and CK_c respectively, unless specifically stated other-
wise.
• Complete functionality may be described throughout the entire document; any page
or diagram may have been simplified to convey a topic and may not be inclusive of all
requirements.
• Any specific requirement takes precedence over a general statement.
• Any functionality not specifically stated here within is considered undefined, illegal,
and not supported, and can result in unknown operation.
• Addressing is denoted as BG[n] for bank group, BA[n] for bank address, and A[n] for
row/col address.
• The NOP command is not allowed, except when exiting maximum power savings
mode or when entering gear-down mode, and only a DES command should be used.
• Not all features described within this document may be available on the rev. A (first)
version.
• Not all specifications listed are finalized industry standards; best conservative esti-
mates have been provided when an industry standard has not been finalized.
• Although it is implied throughout the specification, the DRAM must be used after V_DD
has reached the stable power-on level, which is achieved by toggling CKE at least once
every 8192 × ^tREFI. However, in the event CKE is fixed HIGH, toggling CS_n at least
once every 8192 × ^tREFI is an acceptable alternative. Placing the DRAM into self re-
fresh mode also alleviates the need to toggle CKE.
• Not all features designated in the data sheet may be supported by earlier die revisions
due to late definition by JEDEC.
Definitions of the Device-Pin Signal Level
• HIGH: A device pin is driving the logic 1 state.
• LOW: A device pin is driving the logic 0 state.
• High-Z: A device pin is tri-state.
• ODT: A device pin terminates with the ODT setting, which could be terminating or tri-
state depending on the mode register setting.
Definitions of the Bus Signal Level
• HIGH: One device on the bus is HIGH, and all other devices on the bus are either ODT
or High-Z. The voltage level on the bus is nominally V _DDQ.
• LOW: One device on the bus is LOW, and all other devices on the bus are either ODT
or High-Z. The voltage level on the bus is nominally V_OL(DC) if ODT was enabled, or
V_SSQ if High-Z.
• High-Z: All devices on the bus are High-Z. The voltage level on the bus is undefined as
the bus is floating.
• ODT: At least one device on the bus is ODT, and all others are High-Z. The voltage lev-
el on the bus is nominally V_DDQ.
CCMTD-1725822587-10418
4gb_auto_ddr4_sdram_z90b.pdf - Rev. D 01/17 EN
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