MT9VDDT3272AG Datasheet, PDF (4/27 Pages) Micron Technology – DDR SDRAM UNBUFFERED DIMM

128MB, 256MB, 512MB (x72, ECC, SR), PC3200
184-Pin DDR SDRAM UDIMM
Table 5: Pin Descriptions
Pin numbers may not correlate with symbols; ; Refer to Pin Assignment Tables on page 3 for more information
PIN NUMBERS
63, 65, 154
SYMBOL
WE#, CAS#, RAS#
16, 17, 75, 76, 137, 138
CK0, CK0#, CK1,
CK1#, CK2, CK2#
21
CKE0
157
S0#
52, 59
BA0, BA1
27, 29, 32, 37, 41, 43, 48,
115 (256MB, 512MB), 118,
122, 125, 130, 141
A0–A11
(128MB)
A0–A12
(256MB, 512MB)
44, 45, 49, 51, 134, 135,
142, 144
97, 107, 119, 129, 149, 159,
169, 177
5, 14, 25, 36, 56, 67, 78, 86
CB0–CB7
DM0–DM7
DQS0-DQS7
TYPE
DESCRIPTION
Input
Input
Input
Input
Input
Input
Input/Output
Command Inputs: WE#, RAS#, and CAS# (along with S#)
define the command being entered.
Clocks: CK and CK# are differential clock inputs. All
address and control input signals are sampled on the
crossing of the positive edge of CK and negative edge of
CK#. Output data (DQs and DQS) is referenced to the
crossings of CK and CK#.
Clock Enable: CKE activates (HIGH) and deactivates (LOW)
internal clock signals, device input buffers, and output
drivers. Deactivating the clock provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all device
banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any
device bank). CKE is synchronous for all functions except
for disabling outputs, which is achieved asynchronously.
CKE must be maintained HIGH throughout read and
write accesses. Input buffers (excluding CK, CK# and CKE)
are disabled during POWERDOWN. Input buffers
(excluding CKE) are disabled during SELF REFRESH. CKE is
an SSTL_2 input but will detect an LVCMOS LOW level
after VDD is applied and until CKE is first brought HIGH.
After CKE has been brought HIGH, it is an SSTL_2 input
only.
Chip Select: S# enables (registered LOW) and disable
(registered HIGH) the command decoder. All commands
are masked when S# is registered HIGH. S# is considered
part of the command code.
Bank Addresses: BA0 and BA1 define to which device
bank an ACTIVE, READ, WRITE or PRECHARGE command
is being applied.
Address Inputs: Sampled during the ACTIVE command
(row-address) and READ/WRITE command (column-
address, with A10 defining auto precharge) to select one
location out of the memory array in the respective device
device bank. A10 is sampled during a PRECHARGE
command to determine whether the PRECHARGE applies
to one device bank (A10 LOW) or all device banks (A10
HIGH). The address inputs also provide the op-code
during a MODE REGISTER SET command.
Data I/Os: Check bits.
Input
Input/Output
Data Write Mask: DM LOW allows WRITE operation. DM
HIGH blocks WRITE operation. DM lines do not affect
READ operation.
Data Strobe: Output with READ data, input with WRITE
data. DQS is edge-aligned with READ data, centered in
WRITE data. Used to capture data.
pdf: 09005aef80a43e7d, source: 09005aef80a43d77
DDA9C16_32_64x72AG.fm - Rev. B 9/04 EN
4
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©2004 Micron Technology, Inc.