MT9VDDT3272AG Datasheet, PDF (24/27 Pages) Micron Technology – DDR SDRAM UNBUFFERED DIMM

128MB, 256MB, 512MB (x72, ECC, SR), PC3200
184-Pin DDR SDRAM UDIMM
Table 19: Serial Presence-Detect EEPROM DC Operating Conditions
All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V
PARAMETER/CONDITION
SUPPLY VOLTAGE
INPUT HIGH VOLTAGE: Logic 1; All inputs
INPUT LOW VOLTAGE: Logic 0; All inputs
OUTPUT LOW VOLTAGE: IOUT = 3mA
INPUT LEAKAGE CURRENT: VIN = GND to VDD
OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD
STANDBY CURRENT: SCL = SDA = VDD - 0.3V; All other inputs = VDD OR VSS
POWER SUPPLY CURRENT: SCL clock frequency = 100 KHz
SYMBOL
VDD
VIH
VIL
VOL
ILI
ILO
ISB
ICC
MIN
MAX
2.3
3.6
VDD x 0.7 VDD + 0.5
-1
VDD x 0.3
–
0.4
–
10
–
10
–
30
–
2
UNITS
V
V
V
V
µA
µA
µA
mA
Table 20: Serial Presence-Detect EEPROM AC Operating Conditions
All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V
PARAMETER/CONDITION
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
SDA and SCL fall time
Data-in hold time
Start condition hold time
Clock HIGH period
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
SDA and SCL rise time
SCL clock frequency
Data-in setup time
Start condition setup time
Stop condition setup time
WRITE cycle time
SYMBOL
t_AA
t_BUF
t_DH
t_F
t_HD:DAT
t_HD:STA
t_HIGH
t_I
t_LOW
t_R
f_SCL
t_SU:DAT
t_SU:STA
t_SU:STO
t_WRC
MIN
0.2
1.3
200
0
0.6
0.6
1.3
100
0.6
0.6
MAX
0.9
300
50
0.3
400
10
UNITS
µs
µs
ns
ns
µs
µs
µs
ns
µs
µs
KHz
ns
µs
µs
ms
NOTES
1
2
2
3
4
NOTE:
1. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL = 1 and the falling or rising
edge of SDA.
2. This parameter is sampled.
3. For a reSTART condition, or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (^tWRC) is the time from a valid stop condition of a write sequence to the end of
the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA
remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address.
pdf: 09005aef80a43e7d, source: 09005aef80a43d77
DDA9C16_32_64x72AG.fm - Rev. B 9/04 EN
24
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©2004 Micron Technology, Inc.