MT9VDDT3272AG Datasheet, PDF (19/27 Pages) Micron Technology – DDR SDRAM UNBUFFERED DIMM

128MB, 256MB, 512MB (x72, ECC, SR), PC3200
184-Pin DDR SDRAM UDIMM
(^tQH = ^tHP - ^tQHS). The data valid window derates
in direct proportion to the clock duty cycle and a
practical data valid window can be derived. The
clock is allowed a maximum duty cycle variation of
45/55, beyond which functionality is uncertain.
23. Each byte lane has a corresponding DQS.
24. This limit is actually a nominal value and does not
result in a fail value. CKE is HIGH during
REFRESH command period (^tRFC [MIN]) else
CKE is LOW (i.e., during standby).
25. To maintain a valid level, the transitioning edge of
the input must:
a. Sustain a constant slew rate from the current
AC level through to the target AC level, VIL(AC)
or VIH(AC).
b)Reach at least the target AC level.
c)After the AC target level is reached, continue to
maintain at least the target DC level, VIL(DC) or
VIH(DC).
26. CK and CK# input slew rate must be ≥ 1V/ns (≥
2V/ns if measured differentially).
27. DQ and DM input slew rates must not deviate from
DQS by more than 10 percent. DQ/DM/DQS slew
rates less than 0.5 V/ns are not allowed. If slew rate
exceeds 4 V/ns, functionality is uncertain.
28. VDD must not vary more than 4 percent if CKE is
not active while any device bank is active.
29. The clock is allowed up to ±150ps of jitter. Each
timing parameter is allowed to vary by the same
amount.
30. ^tHP (MIN) is the lesser of ^tCL minimum and ^tCH
minimum actually applied to the device CK and
CK# inputs, collectively during bank active.
31. READs and WRITEs with auto precharge are not
allowed to be issued until ^tRAS (MIN) can be satis-
fied prior to the internal precharge command
being issued.
32. Any positive glitch must be less than 1/3 of the
clock cycle and not more than +400mV or 2.9V,
whichever is less. Any negative glitch must be less
than 1/3 of the clock cycle and not exceed either -
300mV or 2.4V, whichever is more positive. The
DC average cannot go below 2.5V minimum.
33. Normal Output Drive Curves:
a. The full variation in driver pull-down current
from minimum to maximum process, temper-
ature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 7,
Pull-Down Characteristics.
b)The variation in driver pull-down current
within nominal limits of voltage and tempera-
ture is expected, but not guaranteed, to lie
within the inner bounding lines of the V-I curve
of Figure 7, Pull-Down Characteristics.
c)The full variation in driver pull-up current from
minimum to maximum process, temperature and
voltage will lie within the outer bounding lines of
the V-I curve of Figure 8, Pull-Up Characteristics.
d)The variation in driver pull-up current within
nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within the
inner bounding lines of the V-I curve of Figure 8,
Pull-Up Characteristics.
e)The full variation in the ratio of the maximum to
minimum pull-up and pull-down current
should be between 0.71 and 1.4, for device
drain-to-source voltages from 0.1V to 1.0V, and
at the same voltage and temperature.
f ) The full variation in the ratio of the nominal
pull-up to pull-down current should be unity
±10 percent, for device drain-to-source voltages
from 0.1V to 1.0V.
Figure 7: Pull-Down Characteristics
160
140
Maximum
120
100
Nominal ^high
80
Nominal ^low
60
40
Minimum
20
0
0.0
0.5
1.0
1.5
2.0
2.5
VOUT (V)
Figure 8: Pull-Up Characteristics
0
-20
Maximum
-40
-60
Nominal high
-80
-100
-120
Nominal _low
-140
-160
Minimum
-180
-200
0.0
0.5
1.0
1.5
2.0
2.5
VDDQ - VOUT (V)
pdf: 09005aef80a43e7d, source: 09005aef80a43d77
DDA9C16_32_64x72AG.fm - Rev. B 9/04 EN
19
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