MT9VDDT3272AG Datasheet, PDF (10/27 Pages) Micron Technology – DDR SDRAM UNBUFFERED DIMM

128MB, 256MB, 512MB (x72, ECC, SR), PC3200
184-Pin DDR SDRAM UDIMM
BA1 = 0) and will retain the stored information until it
is programmed again or the device loses power. The
enabling of the DLL should always be followed by a
LOAD MODE REGISTER command to the mode regis-
ter (BA0/BA1 both low) to reset the DLL.
The extended mode register must be loaded when
all device banks are idle and no bursts are in progress,
and the controller must wait the specified time before
initiating any subsequent operation. Violating either
of these requirements could result in unspecified oper-
ation.
DLL Enable/Disable
The DLL must be enabled for normal operation.
DLL enable is required during power-up initialization
and upon returning to normal operation after having
disabled the DLL for the purpose of debug or evalua-
tion. (When the device exits self refresh mode, the DLL
is enabled automatically.) Any time the DLL is
enabled, 200 clock cycles must occur before a READ
command can be issued.
Figure 6: Extended Mode Register
Definition Diagram
128MB Module
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
13 12 11 10 9 8 7 6 5 4 3 2² 1 0 _{Extended Mode}
01 11
Operating Mode
DS DLL Register (Ex)
256MB, 512MB Modules
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
14 13 12 11 10 9 8 7 6 5 4 3 2² 1 0
01 11
Operating Mode
DS DLL
Extended Mode
Register (Ex)
E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2²
0 0 0 0 0 0 00 0 0 0
– – – – – – –– – – –
E1, E0
Valid
–
E0
DLL
0
Enable
1
Disable
E1 Drive Strength
0
Normal
Operating Mode
Reserved
Reserved
NOTE:
1. BA1 and BA0 (E13 and E12 for 128MB or E14 and E13
for 256MB, 512MB) must be “0, 1” to select the
Extended Mode Register (vs. the base Mode Register).
2. The QFC# option is not supported.
pdf: 09005aef80a43e7d, source: 09005aef80a43d77
DDA9C16_32_64x72AG.fm - Rev. B 9/04 EN
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©2004 Micron Technology, Inc.