MT9VDDT3272AG Datasheet, PDF (11/27 Pages) Micron Technology – DDR SDRAM UNBUFFERED DIMM

128MB, 256MB, 512MB (x72, ECC, SR), PC3200
184-Pin DDR SDRAM UDIMM
Commands
Table 8, Commands Truth Table, and Table 9, DM
Operation Truth Table, provide a general reference of
available commands. For a more detailed description
of commands and operations, refer to the 128Mb,
256Mb, or 512Mb DDR SDRAM component data
sheets.
Table 8: Commands Truth Table
DESELECT and NOP are functionally interchangeable; all states and sequences not shown are illegal or reserved
NAME (FUNCTION)
DESELECT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH (Enter self refresh mode)
LOAD MODE REGISTER
CS# RAS# CAS# WE#
H
X
X
X
L
H
H
H
L
L
H
H
L
H
L
H
L
H
L
L
L
H
H
L
L
L
H
L
L
L
L
H
L
L
L
L
ADDR
X
X
Bank/Row
Bank/Col
Bank/Col
X
Code
X
Op-Code
NOTES
1
1
2
3
3
4
5
6, 7
8
NOTE:
1. DESELECT and NOP are functionally interchangeable.
2. BA0–BA1 provide device bank address and A0–A11 (128MB) or A0–A12 (256MB, 512MB) provide device row address.
3. BA0–BA1 provide device bank address; A0–A9 (128MB, 256MB) or A0–A9, A11 (512MB) provide device column address;
A10 HIGH enables the auto precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature.
4. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for read
bursts with auto precharge enabled and for write bursts.
5. A10 LOW: BA0–BA1 determine which device bank is precharged. A10 HIGH: all device banks are precharged and BA0–
BA1 are “Don’t Care.”
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls device row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. BA0-BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register; BA0 =
1, BA1 = 0 select extended mode register; other combinations of BA0–BA1 are reserved). A0–A11 (128MB) or A0–A12
(256MB, 512MB) provide the op-code to be written to the selected mode register.
Table 9: DM Operation Truth Table
Used to mask write data; provided coincident with the corresponding data
WRITE Enable
WRITE Inhibit
NAME (FUNCTION)
DM
DQS
L
Valid
H
X
pdf: 09005aef80a43e7d, source: 09005aef80a43d77
DDA9C16_32_64x72AG.fm - Rev. B 9/04 EN
11
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©2004 Micron Technology, Inc.