MT9VDDT3272AG Datasheet, PDF (20/27 Pages) Micron Technology – DDR SDRAM UNBUFFERED DIMM

128MB, 256MB, 512MB (x72, ECC, SR), PC3200
184-Pin DDR SDRAM UDIMM
34. The voltage levels used are derived from a mini-
mum VDD level and the referenced test load. In
practice, the voltage levels obtained from a prop-
erly terminated bus will provide significantly dif-
ferent voltage values.
35. VIH overshoot: VIH (MAX) = VDDQ+1.5V for a pulse
width ≤ 3ns and the pulse width can not be greater
than 1/3 of the cycle rate. VIL undershoot: VIL (MIN)
= -1.5V for a pulse width ≤ 3ns and the pulse width
can not be greater than 1/3 of the cycle rate.
36. VDD and VDDQ must track each other.
37. ^tHZ (MAX) will prevail over ^tDQSCK (MAX) +
t_{RPST (MAX) condition.} t_{LZ (MIN) will prevail}
over ^tDQSCK (MIN) + ^tRPRE (MAX) condition.
38. ^tRPST end point and ^tRPRE begin point are not
referenced to a specific voltage level but specify
when the device output is no longer driving
(^tRPST), or begins driving (^tRPRE).
39. During initialzation, VDDQ, VTT, and VREF must be
equal to or less than VDD + 0.3V. Alternatively, VTT
may be 1.35V maximum during power up, even if
VDD/VDDQ are 0.0V, provided a minimum of 42
ohms of series resistance is used between the VTT
supply and the input pin.
40. The current Micron part operates below the slow-
est JEDEC operating frequency of 83 MHz. As
such, future die may not reflect this option.
41. For -40B modules, IDD3N is specified to be 35mA
per DDR SDRAM device at 100 MHz.
42. Random addressing changing and 50 percent of
data changing at every transfer.
43. Random addressing changing and 100 percent of
data changing at every transfer.
44. CKE must be active (high) during the entire time a
refresh command is executed. That is, from the
time the AUTO REFRESH command is registered,
CKE must be active at each rising clock edge, until
t_{REF later.}
45. IDD2N specifies the DQ, DQS and DM to be driven
to a valid high or low logic level. IDD2Q is similar
to IDD2F except IDD2Q specifies the address and
control inputs to remain stable. Although IDD2F,
IDD2N, and IDD2Q are similar, IDD2F is “worst
case.”
46. Whenever the operating frequency is altered, not
including jitter, the DLL is required to be reset.
This is followed by 200 clock cycles.
47. Leakage number reflects the worst case leakage
possible through the module pin, not what each
memory device contributes.
48. When an input signal is HIGH or LOW, it is
defined as a steady state logic HIGH or LOW.
pdf: 09005aef80a43e7d, source: 09005aef80a43d77
DDA9C16_32_64x72AG.fm - Rev. B 9/04 EN
20
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©2004 Micron Technology, Inc.