N25Q256A11ESF40F Datasheet, PDF (35/87 Pages) Micron Technology – Micron Serial NOR Flash Memory

1.8V, 256Mb: Multiple I/O Serial Flash Memory
READ REGISTER and WRITE REGISTER Operations
fect. If S# is not driven HIGH, the command is not executed, flag status register error
bits are not set, and the write enable latch remains set to 1.
Figure 12: WRITE LOCK REGISTER Command
Extended
C
0
7
8
C_x
LSB
A[MIN]
DQ[0]
Command
D_IN
D_IN
D_IN
D_IN
MSB
A[MAX]
MSB
LSB
D_IN
D_IN
D_IN
D_IN
D_IN
Dual
C
0
3
4
C_x
LSB
A[MIN]
DQ[1:0]
Command
D_IN
D_IN
D_IN
MSB
A[MAX]
MSB
LSB
D_IN
D_IN
Quad
C
0
1
2
C_x
DQ[3:0]
Command
MSB
LSB
A[MAX]
A[MIN]
D_IN
MSB
LSB
D_IN
D_IN
Note:
1. For extended SPI protocol, C_x = 7 + (A[MAX] + 1).
For dual SPI protocol, C_x = 3 + ((A[MAX] + 1)/2).
For quad SPI protocol, C_x = 1 + ((A[MAX] + 1)/4).
CLEAR FLAG STATUS REGISTER Command
To execute the CLEAR FLAG STATUS REGISTER command and reset the error bits
(erase, program, and protection), S# is driven LOW. For extended SPI protocol, the com-
mand code is input on DQ0. For dual SPI protocol, the command code is input on
DQ[1:0]. For quad SPI protocol, the command code is input on DQ[3:0]. The operation
is terminated by driving S# HIGH at any time.
PDF: 09005aef846a804a
n25q_256mb_1_8V_65nm.pdf - Rev. G 2/2012 EN
35
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