N25Q256A11ESF40F Datasheet, PDF (29/87 Pages) Micron Technology – Micron Serial NOR Flash Memory

1.8V, 256Mb: Multiple I/O Serial Flash Memory
Command Definitions
Table 16: Command Set (Continued)
Note 1 applies to entire table
Command
Code
ONE-TIME PROGRAMMABLE (OTP) Operations
READ OTP ARRAY
4Bh
PROGRAM OTP ARRAY
42h
4-BYTE ADDRESS MODE Operations
ENTER 4-BYTE ADDRESS MODE
B7h
EXIT 4-BYTE ADDRESS MODE
E9h
DEEP POWER-DOWN Operations
ENTER DEEP POWER-DOWN
B9h
RELEASE from DEEP POWER-DOWN
ABh
Extended
Yes
Yes
Yes
Dual
I/O
Yes
Yes
Yes
Quad
I/O
Yes
Yes
Data
Bytes
1 to 64
0
Notes
5
4
2, 13
Yes
0
2
Notes: 1. Yes in the protocol columns indicates that the command is supported and has the same
functionality and command sequence as other commands marked Yes.
2. Address bytes = 0. Dummy clock cycles = 0.
3. Address bytes = 3. Dummy clock cycles default = 8.
4. Address bytes default = 3; address bytes = 4 (extended address). Dummy clock cycles = 0.
5. Address bytes default = 3; address bytes = 4 (extended address). Dummy clock cycles de-
fault = 8. Dummy clock cycles default = 10 when quad SPI protocol is enabled. Dummy
clock cycles are configurable by the user.
6. Address bytes default = 3; address bytes = 4 (extended address). Dummy clock cycles de-
fault = 6. Dummy clock cycles default = 8 when quad SPI protocol is enabled. Dummy
clock cycles are configurable by the user.
7. Address bytes default = 3; address bytes = 4 (extended address). Dummy clock cycles de-
fault = 8. Dummy clock cycles are configurable by the user.
8. Address bytes = 4. Dummy clock cycles = 0.
9. Address bytes = 4. Dummy clock cycles default = 8. Dummy clock cycles default = 10
when quad SPI protocol is enabled. Dummy clock cycles are configurable by the user.
10. Address bytes = 4. Dummy clock cycles default = 10. Dummy clock cycles is configurable
by the user.
11. When the device is in dual SPI protocol, the command can be entered with any of these
three codes. The different codes enable compatibility between dual SPI and extended
SPI protocols.
12. When the device is in quad SPI protocol, the command can be entered with any of these
three codes. The different codes enable compatibility between quad SPI and extended
SPI protocols.
13. The WRITE ENABLE command must be issued first before this command can be execu-
ted.
PDF: 09005aef846a804a
n25q_256mb_1_8V_65nm.pdf - Rev. G 2/2012 EN
29
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.