MT41J128M16JT-125K Datasheet, PDF (209/211 Pages) Micron Technology – DDR3 SDRAM MT41J512M4 64 Meg x 4 x 8 Banks MT41J256M8 32 Meg x 8 x 8 Banks MT41J128M16 16 Meg x 16 x 8 Banks

2Gb: x4, x8, x16 DDR3 SDRAM
Asynchronous to Synchronous ODT Mode Transition (Power-
Down Exit)
Asynchronous to Synchronous ODT Mode Transition (Short CKE Pulse)
If the time in the precharge power-down or idle states is very short (short CKE LOW
pulse), the power-down entry and power-down exit transition periods overlap. When
overlap occurs, the response of the DRAM’s R_TT to a change in the ODT state can be
synchronous or asynchronous from the start of the power-down entry transition period
to the end of the power-down exit transition period, even if the entry period ends later
than the exit period.
If the time in the idle state is very short (short CKE HIGH pulse), the power-down exit
and power-down entry transition periods overlap. When this overlap occurs, the re-
sponse of the DRAM’s R_TT to a change in the ODT state may be synchronous or asyn-
chronous from the start of power-down exit transition period to the end of the power-
down entry transition period.
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN
209
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