MT41J128M16JT-125K Datasheet, PDF (199/211 Pages) Micron Technology – DDR3 SDRAM MT41J512M4 64 Meg x 4 x 8 Banks MT41J256M8 32 Meg x 8 x 8 Banks MT41J128M16 16 Meg x 16 x 8 Banks

Table 90: Synchronous ODT Parameters
Symbol
ODTLon
ODTLoff
ODTH4
ODTH8
t_AON
t_AOF
Description
Begins at
ODT synchronous turn-on delay
ODT registered HIGH
ODT synchronous turn-off delay
ODT registered HIGH
ODT minimum HIGH time after ODT ODT registered HIGH or write regis-
assertion or WRITE (BC4)
tration with ODT HIGH
ODT minimum HIGH time after WRITE Write registration with ODT HIGH
(BL8)
ODT turn-on relative to ODTLon
completion
Completion of ODTLon
ODT turn-off relative to ODTLoff
completion
Completion of ODTLoff
Defined to
R_TT(ON) ±^tAON
R_TT(OFF) ±^tAOF
ODT registered LOW
ODT registered LOW
R_TT(ON)
R_TT(OFF)
Definition for All
DDR3 Speed Bins
CWL + AL - 2
CWL +AL - 2
4^tCK
6^tCK
See Table 56
(page 76)
0.5^tCK ± 0.2^tCK
Unit
t_CK
t_CK
t_CK
t_CK
ps
t_CK
Figure 113: Synchronous ODT
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
CK#
CK
CKE
AL = 3
AL = 3
CWL - 2
ODT
ODTH4 (MIN)
ODTLoff = CWL + AL - 2
ODTLon = CWL + AL - 2
t_{AON (MIN)}
t_{AOF (MIN)}
R_TT
R_TT,nom
t_{AON (MAX)}
t_{AOF (MAX)}
Transitioning
Don’t Care
Note: 1. AL = 3; CWL = 5; ODTLon = WL = 6.0; ODTLoff = WL - 2 = 6. R_TT,nom is enabled.